Distributed switching and telephone conferencing system

• US 5,276,678 A
• Filed: 06/18/1990
• Issued: 01/04/1994
• Est. Priority Date: 06/18/1990
• Status: Expired due to Fees

• Current Assignee: Hughes Aircraft Company (Rtx Corporation)
• Original Assignee: Intelect BV
• Inventors: Munson, Verne E., Onaka, Peter M., Stevens, Christopher J., Hendrickson, Herbert C.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): TON, DANG T
• Application Number:
  US07/539,787
• Time in Patent Office: 1,296 Days
• Field of Search: 370/110.1, 370/60, 370/58.1, 370/85.1, 370/44.1, 370/58.2, 370/58.3, 370/85.9, 379/202, 379/17, 379/158
• US Class Current: 370/267
• CPC Class Codes: H04M 3/561 by multiplexing
• CPC Class Codes: H04M 3/562 where the conference facilities are distributed
• CPC Class Codes: H04Q 11/0407 using a stored programme control
• CPC Class Codes: H04Q 2213/13003 Constructional details of switching devices
• CPC Class Codes: H04Q 2213/13093 Personal computer, PC
• CPC Class Codes: H04Q 2213/13106 Microprocessor, CPU
• CPC Class Codes: H04Q 2213/1324 Conference call
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/13299 Bus

Abstract

A communication system having full call processing capabilities in the user ports, each port being connected to a TDM collection bus and a TDM distribution bus. A bus controller terminates the collection bus on which voice words are deposited in time slots by the respective user ports, the voice words being realigned and transmitted by the bus controller on the TDM distribution bus. Each user port is assigned a time slot and can thus communicated simultaneously with one or more other user ports, such as during a two-way telephone conversation or a multiple party conference call. A memory in each user port combines plural voice words obtained from respective TDM time slots of conference participants, and combines such voice words into a composite signal representative of all the other conferees. The conference circuit of each user port combines the voice words of all the other participating ports over a frame period, except its own voice word, and thus the composite voice word of each user port is different.

Claims

1. A digital conference circuit arrangement for combining audio information from plural sources, comprising:

a plurality of user ports each adapted to transmit and receive audio signals from sound reproducing apparatus, each said user port including a digital word combining circuit for summing plural digital words to achieve a composite digital word;

a common TDM bus for interconnecting each user port, said TDM bus including a time slot assigned to each user port, ones of said time slots carrying digital words representative of audio signals, and address information identifying the user ports; and

each said user port including a processor and programmable support circuits, said processor being programmed to establish a conference by transmitting on the TDM bus on an assigned time slot addresses of all the other ports to participate in the conference, and in response to an acknowledgement received in other time slots of the TDM bus, said process programs said support circuits with time slot information so that digital words of the other ports participating in the conference are coupled to said digital word combining circuit to achieve said composite digital words, and said support circuits converting the composite digital words to audio sounds and coupling the audio sounds to the sound reproducing apparatus.

2. The conference circuit of claim 1, further including a circuit in each user port for comparing address bits carried by said TDM bus with other digital bits identifying that port, and on a match thereof, identifying the time slot carrying the matched address to determine another user port desiring to establish a conference.

3. The conference circuit of claim 1, wherein said TDM bus includes a collection bus for receiving voice words from each user port, and a distribution bus for transferring voice words to each user port.

4. The conference circuit of claim 3, further including a circuit connecting the collection bus to the distribution bus to resynchronize the time slots.

5. The conference circuit of claim 1, wherein said TDM bus has a time slot dedicated to each user port.

6. The conference circuit of claim 1, further including a circuit for storing data representative of summations of substantially all combinations of digital word combinations to be combined.

7. The conference circuit of claim 6, further including in each user port a register for successively storing a composite of plural digital words in a frame interval.

8. The conference circuit of claim 7, further including a circuit for appending to an output of said register another digital word, the appended combination defining an address for accessing a memory which stores the summation data.

9. The conference circuit of claim 1, further including a bit carried by said TDM bus for defining the transmission of nonvoice data, and means for the digital word circuit when said bit is carried by the TDM bus.

10. The conference circuit of claim 1, wherein said TDM bus includes a TDM collection bus and a TDM distribution bus, and further includes a U-turn repeater having an input connected to the collection bus and an output connected to the distribution bus for regenerating bits.

11. The conference circuit of claim 1, wherein said TDM bus has time slots in excess of the number of user ports, said excess time slots being adapted for carrying data to a bus control circuit which controls timing of the TDM bus.

12. The conference circuit of claim 11, further including means for inserting programming data in said excess time slots and for downloading data to each user port.

13. The conference circuit of claim 11, further including means for inserting data representative of call progress tones in said excess time slots.

14. The conference circuit of claim 1, wherein said digital word combining circuit is adapted to combine a null data word with data words of a single time slot during a two-way conversation.

15. The conference circuit of claim 6, wherein said digital word combining circuit adds nonlinear digital words and provides a corresponding nonlinear composite digital word.

16. The conference circuit of claim 1, wherein said digital words comprise voice signals converted to multibit words.

17. The conference circuit of claim 1, wherein digital words representative of tones are processed by the combining circuit and added with null digital words to pass tone digital words substantially unchanged.

18. The conference circuit of claim 1, further including a memory which is programmable with data associated with each time slot, and means for reading the memory in synchronization with the TDM bus time slots, an output of the memory controlling whether or not data words of each time slot are to be combined by said combining circuit.

19. The conference circuit of claim 1, further including in each port, means for preventing the digital words generated by that port from being combined with digital words of other ports by the combining circuit of that port.

20. The conference circuit of claim 1, wherein said TDM bus includes bit positions in each time slot for identifying different bus cycles, one cycle being utilized in initiating a conference, wherein other bits of the time slot include address information of the ports to be involved in the conference.

21. The conference circuit of claim 20, wherein each said port includes a circuit responsive to a bus cycle having address information for matching such address information with port identity information, and on a match, transmitting on a TDM bus time slot data corresponding to an acknowledgement.

22. The conference circuit of claim 20, wherein one said bus cycle which includes the transmission of address information precedes a bus cycle in which digital words are transmitted in the respective TDM bus time slots.

23. The conference circuit of claim 1, wherein each said process includes a table in which the other ports are uniquely associated with respective time slots.

24. The conference circuit of claim 1, wherein each said processor includes a status table in which data is stored corresponding to an operating status of each port.

25. The conference circuit of claim 1, wherein time slot bits of the TDM bus carry status information of each said port.

26. In a digital telecommunication system, a method for conferencing a plurality of digital signals representative of voice communications, comprising the steps of:

providing a memory having stored therein summation results of bits defined by signals applied to address inputs thereof;

(a) selecting from a TDM bus a digital word defining a portion of an audio sound to be conferenced;

(b) coupling the digital word to an address input of the memory for use in reading the memory;

(c) temporarily storing memory readout data;

(d) using the memory readout data together with a subsequent digital word selected from the TDM bus for accessing the memory to derive a summation signal; and

(e) carrying out steps (a) through (d) for digital words received on the TDM bus in selected TDM bus time slots to define a final summation signal which is a composite of the digital words to be conferenced in a TDM frame interval.

27. The method of claim 26, further including combining an initial digital word of M-bits with a subsequent digital word of N-bits by appending the M-bit word with the N-bit word to define an address with M+N bits.

28. The method of claim 26, further including storing the final summation signal and feeding said final summation signal back to an input of the memory.

29. The method of claim 26, further including adding the digital words together by accessing the memory with the words and reading out the summation digital signal.

30. The method of claim 26, further including converting the final summation signal of said memory once during each frame interval to an analog signal for use in driving sound reproducing equipment using the analog signal.

31. The method of claim 26, wherein said memory defines a first memory, and further including storing in a second memory digital bits indicating whether or not digital words of the time slots are to be used in accessing the first memory.

32. The method of claim 31, further including reading the second memory in synchronization with the TDM bus time slots and using the output of the second memory for allowing digital words from the time slots to be used in accessing the first memory, and preventing the digital words from the time slots not to be conferenced from being used in accessing the first memory.

33. The method of claim 26, further including carrying out said conferencing steps in each of a plurality of user ports connected to the TDM bus and participating in a conference.

34. The method of claim 33, further including setting up a conference by defining which time slots are conference participants by using a microprocessor in each user port, and carrying out the conferencing steps with high speed circuit without the microprocessor.

35. The method of claim 26, further including storing the summation signal in a register, and resetting the register so that at the beginning of the specified frame interval, the summation signal used with the initial digital word is a null value.

36. A telecommunication conference circuit for combining voice information from plural sources, comprising:

at least a pair of user port circuits adapted to communicate audio signals with respective audio sound apparatus;

a TDM bus arrangement interconnecting each said user port, said TDM bus arrangement including duplicated TDM collection buses on which each user port transmits in respective dedicated time slots digital voice words, and duplicated TDM distribution buses on which each user port receives in respective dedicated time slots digital voice words;

controller circuits for controlling the duplicated TDM distribution and collection buses, said controller circuits functioning to maintain one TDM distribution bus active and one in a stand-by status, and to maintain one TDM collection bus active and one in a stand-by status, said user ports, transmitting digital voice words on each TDM collection bus and receiving digital voice words from each TDM distribution bus;

each user port including circuits for initiating a conference and setting up a conference by driving a duplicated TDM collection bus time slot with address information identifying another user port with which a conference connection is to be established, circuits for receiving acknowledgement information on other time slots of the duplicated TDM distribution buses from other user ports, a bus driver circuit for driving the duplicated TDM collection buses during a respective dedicated time slot with digital voice words representative of audio sounds, a bus receiver for receiving digital voice words of other conferenced ports from the duplicated TDM distribution buses, a circuit for specifying the time slots of the duplicated TDM distribution buses which are associated with user ports participating in a conference, a digital combiner for receiving digital voice words only from other user ports participating in the conference and for combining said digital voice words into a composite word for transferral to the audio sound apparatus.

37. The conference circuit of claim 36, further including in each user port means for converting audio sounds input into each user port to corresponding digital voice words and and for transmitting the digital voice words on the TDM collection bus, and means for combining voice words received from the TDM distribution bus such that the combining of voice words in a port does not include voice words generated by that port.

38. The conference circuit of claim 36, wherein said digital combiner comprises a memory storing a summation result of each combination of digital voice words which can be generated by the user ports.

39. The conference circuit of claim 38, wherein said memory stores summations of digital voice words encoded according to a nonlinear format.

40. The conference circuit of claim 36, further including a bus controller common to all user ports for providing timing signals for the duplicated TDM collection buses and the duplicated TDM distribution buses.

41. The conference circuit of claim 40, wherein said bus controller includes a circuit for receiving digital voice words in time slots on the TDM collection bus and for resynchronizing the digital voice words and driving the TDM distribution bus with resynchronized digital voice words.

42. The conference circuit of claim 36, further including duplicated controller circuits, one controller circuit for controlling one TDM distribution bus and one TDM collection bus, and another controller circuit for controlling the other TDM distribution bus and the other TDM collection bus.

43. A digital conferencing circuit for use in a time division multiplex (TDM) system, comprising:

a combining memory having prestored therein summation results of signals presented to an input of the memory, said combining memory receiving addresses from the TDM system on an input of the memory;

a result register having an input for receiving summation data output from the memory, an output of said result register being used as an input coupled back to said combining memory; and

a time slot memory storing data associated with each time slot of the TDM system for indicating whether or not a voice word associated with each time slot is to be combined with another voice word, an output of said time slot memory being used to prevent said combining memory from responding to the voice words from the TDM system when said output of said time slot memory comprises a first indication, and to allow combining of the voice words when the time slot memory output comprises a second indication.

44. The digital conferencing circuit of claim 43, further including an input register for latching said voice words therein before being input as addresses to the combining memory.

45. The digital conferencing circuit of claim 44, wherein the output of the time slot memory is used to control the transfer of voice words from the input register to the combining memory.

46. The digital conferencing circuit of claim 45 wherein the time slot memory includes means for forcing the input register to produce an output representative of an analog zero signal.

47. A method for conferencing digitized signals in a time division multiplex (TDM) system, comprising the steps of:

writing a time slot memory with data indicating whether or not various time slots of the TDM system are to participate in a conference;

presenting the digital signals of all TDM time slots to a combining circuit;

reading the time slot memory in synchronization with TDM time slots to derive a memory output; and

controlling the combining circuit with the time slot memory output to combine digital signals of respective time slots when the time slot memory output for the associated time slots comprise a first indication, and preventing the combining of digital signals when the time slot memory output comprises a second indication.

48. The method of claim 47, further including writing the time slot memory with a single digital bit for all time slots, the logic state of the bit indicating whether or not digital signals of the respective time slots are to be combined.

49. The method of claim 47, further including combining digital signals by adding together those digital signals to be conferenced.

50. The method of claim 49, further including adding digital signals which are encoded in a nonlinear manner.

51. The method of claim 47, further including presenting two digital signals to be combined as a composite address to a combining memory, the readout of which is a resultant digital word.

52. The method of claim 51, further including presenting the resultant memory readout to an input of the combining memory together with another digital audio signal from the TDM system to define a subsequent composite memory address, and addressing the combining memory to derive yet another resultant memory readout.

53. The method of claim 52, further including repeating the memory addressing for an entire frame period and using a last resultant memory readout for use in converting to an analog signal.

54. The method of claim 47, further including controlling the combining circuit by sequentially inputting the digital signals of each time slot into a register, and if the digital signal is not to be combined, using the time slot memory output to force the register to produce an output representative of an analog zero signal.

55. In a telecommunication system, a user port for carrying out communications with other similar ports via a TDM bus, comprising:

a bus interface for communicating digital signals with the TDM bus;

a user instrument interface for communicating audio signal with audio transducers;

converting means in said user instrument interface for converting digital signals to analog signals, and vice versa;

an identity uniquely associated with the user port;

a conference memory;

a processor programmed to;

a) initialize high speed hardware circuits to retrieve digital signals from the TDM bus during time slots;

b) select those digital signals associated with the time slots which are to participate in the conference;

c) cause a series of memory addresses to be derived based on the selected digital signals for the conference time slot participants;

d) cause the conference memory to be accessed with said derived memory addresses to produce a composite readout comprising an addition of each of the selected digital signals; and

means for transferring the composite readout to said converting means in said user instrument interface so that said composite readout can be converted to an analog signal.

56. The user port of claim 55, further including a register for temporarily storing the composite readout, and means for combining the composite readout with subsequent digital signals retrieved from the TDM bus to generate the memory addresses.

57. The user port of claim 56, wherein said hardware circuits include means for sequentially generating memory readouts during a frame of time slots, and for each frame said hardware circuits generate a single composite readout which is converted to an analog signal.

58. The user port of claim 55, further including a counter for counting time slots with respect to a reference, the counter output identifying user ports connected to the TDM bus.

59. The user port of claim 58, further including means for resetting the counter with a reference frame signal which precedes each group of time slots.

60. The user port of claim 55, further including a hardware circuit responsive to a request for service of another user port for driving said TDM bus with a status word and an address of the user port to which communications are desired.

61. The user port of claim 60, further including a circuit responsive to a control status word on said TDM bus for signifying user port acceptance of communication with another user port.

62. The user port of claim 55, wherein said bus interface includes an outbound interface for receiving digital signals on a TDM distribution bus, and an inbound interface for transmitting digital signals on a TDM collection bus.

63. A telecommunication system, comprising:

a time division multiplex (TDM) bus for carrying voice words between subscribers associated with the system;

at least three user ports connected to the telecommunication system so as to be able to communicate voice words via the TDM bus, and each said port being dedicated for use with a single subscriber;

a conference circuit in each said user port for combining voice words and for transferring corresponding analog signals to a user associated with the respective ports, one said conference circuit being dedicated for use with each said port; and

a processor in each said user port for controlling the conference circuit to pass voice words therethrough substantially unchanged in a two-way telephone conference and to combine voice words in said conference circuit to produce different resultant voice words in a conference call involving three or more user ports.

64. The communication system of claim 63, wherein said TDM bus includes time slots carrying tones, and wherein said processor controls said conference circuit to pass digital signals therethrough representative of the tones.

65. The communication system of claim 63, wherein said TDM bus includes time slots for carrying voice words, and said conference circuit is connected so that all voice words transferred from said TDM bus to the user ports pass through a respective said conference circuit.

66. The communication system of claim 63, wherein said conference circuit includes a memory in which voice words are utilized to access said memory during conference and non-conference calls to derive other voice words communicated to users of the respective port.

67. A communication system, comprising:

a plurality of user ports serving a plurality of user instruments;

a time division multiplex (TDM) bus connected to each user port, a different time slot of said TDM bus being dedicated to each user port for communicating digital words, whereby a user port always communicates digital words on the same time slot;

a bus timing circuit for providing timing signals to each user port to provide synchronization of each user port to a respective bus time slot;

each user port including;

a bus interface for communicating high speed digital words to and from the TDM bus;

high speed hardware circuits for receiving and transmitting digital words with respect to said user port;

a user instrument interface providing an interface between the user port and an associated subscriber instrument; and

a processor programmed to initialize said hardware circuits for communicating high speed digital words between said bus interface and said user instrument interface, and to monitor status indications of the user instrument, said processor being programmed to respond to requests for service from an instrument connected to the port for communicating with another port by way of the TDM bus to establish a call path, to carry on bidirectional communications between users using the TDM bus, and to terminate the communication by signalling between the respective user ports using the TDM bus.

68. The communication system of claim 67, wherein said TDM bus comprises a TDM collection bus for receiving digital words from each user port, and a TDM distribution bus for delivering digital words to each user port.

69. The communication system of claim 68, further including a synchronizing circuit for receiving digital words from the TDM collection bus and retransmitting digital words resynchronized with corresponding time slots on the TDM distribution bus.

70. The communication system of claim 68, wherein said TDM bus includes conductors for carrying digital words in time slots, and further includes conductors carrying time slot timing signals and framing interval signals.

71. The communication system of claim 70, wherein said bus timing circuit includes means for generating a frame timing signal for said TDM distribution bus, delayed from a frame timing signal of said TDM collection bus.

72. The communication system of claim 67, wherein said bus timing circuit includes a bus control circuit for storing call processing program software, and said bus control circuit has assigned thereto a time slot on the TDM bus for communicating with the user ports.

73. The communication system of claim 72, wherein said bus control circuit is processor controlled to initialize communications with the user ports to download the software thereto in the assigned time slot.

74. The communication system of claim 67, wherein said bus timing circuit includes a bus control circuit having digital call progress tone generators, and said TDM bus carries digitized tone signals to each user port.

75. The communication system of claim 67, wherein said TDM bus includes a conductor for carrying status information of each user port in a time slot, and each user port includes a circuit for monitoring the TDM bus status of the other user ports, and each user port includes a software status table for storing the status of the other user ports.

76. The communication system of claim 72, wherein said bus control circuits are duplicated and further including a UART for providing communications therebetween.

77. The communication system of claim 67, wherein said bus timing circuit defines a bus controller, and further including duplicated bus controllers, and a bi-stable circuit for providing opposite output data states indicating one bus controller as an on-line master and the other bus controller as a standby.

78. In a telecommunication system, a user port for carrying out communications with other similar ports via a TDM bus, said user port comprising:

a bus interface for communicating digital signals with the TDM bus;

a user instrument interface for communicating audio signals with audio transducers;

a converter in said user instrument interface for converting the digital signals to the audio signals, and vice versa;

a processor associated with each said user port and programmed to carry out call processing functions including establishing communications between said user port and said other similar user ports, a memory associated with each said user port and being accessible by a respective said processor, said memory storing busy/idle status indications of each said other similar user ports, said processor being responsive to requests for service from the user instrument interface to complete a call to a destination user port by accessing said memory to determine the status of said destination user port, and if said status indication is busy, said processor returns a busy indication to the user instrument interface, and if said status indication is idle, said processor compels communication via said TDM bus to said destination user port.

79. The user port of claim 78, wherein said TDM bus carries user port status information between each said user port.

80. The user port of claim 78, further including a memory for storing user port identification information for correlating TDM bus time slots with telephone number extension information.

81. The user port of claim 80, wherein said processor is programmed to be responsive to said requests for service for accessing said memory to determine a time slot associated with the destination user port and the status thereof.

82. The user port of claim 78, further including a microprocessor uniquely associated with each said user port for carrying out call processing functions.

83. A communication system, comprising:

a plurality of user ports serving a plurality of user instruments;

duplicated TDM collection buses and duplicated TDM distribution buses defining time division multiplex (TDM) buses connected to each user port, said duplicated TDM collection buses for receiving digital words from each user port, and said duplicated TDM distribution buses for delivering digital words to each user port, and a time slot of said TDM buses being dedicated to each user port for communicating digital words;

a bus timing circuit for providing timing signals to each user port to provide synchronization of each user port to a respective bus time slot; and

each user port including,

a bus interface for communicating high speed digital words to and from the TDM buses,

high speed hardware circuits for receiving and transmitting digital words with respect to said user port,

a user instrument interface providing an interface between the user port and an associated subscriber instrument, and

a processor programmed to initialize said hardware circuits for communicating high speed digital words between said bus interface and said user instrument interface, and to monitor status indications of the user instrument, said processor being programmed to respond to request for service from an instrument connected to the port for communicating with another port by way of the TDM buses to establish a call path, to carry on bidirectional communications between users using the TDM buses, and to terminate the communication by signalling between the respective user ports using the TDM buses.

84. The communication system of claim 83, further including means for synchronizing the duplicated TDM buses.

85. The communication system of claim 83, further including a pair of bus timing circuits for providing timing signals to the respective ports of the TDM buses.

86. The communication system of claim 85, further including means for maintaining synchronizing of timing signals between said bus timing circuits so that if one timing circuit fails, the other can assume control without loss of bus time slot timing.