Circuit arrangement for bit rate adjustment

• US 5,276,688 A
• Filed: 12/10/1992
• Issued: 01/04/1994
• Est. Priority Date: 06/09/1990
• Status: Expired due to Fees

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Urbansky, Ralph
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Jung, Min
• Application Number:
  US07/989,744
• Time in Patent Office: 390 Days
• Field of Search: 370/102, 370/84, 370/105.3, 370/108, 370/112, 375/118, 375/119, 375/120, 375/111, 375/112
• US Class Current: 370/465
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
• CPC Class Codes: H04L 25/05 Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate

Abstract

A circuit arrangement for adjusting the bit rates of two signals of which the higher bit rate signal is structured in frames, includes a buffer memory (2), a write counter and a read counter (6, 8) as well as a phase comparator (7) and a control circuit (10). With these modules the bits of the lower bit rate signal are arranged in the frames of the higher bit rate signal. In addition to these bits negative or positive stuff bits are also inserted in the frames. In order to avoid jitter when the lower bit rate signal is recovered at the receiver end, the phase different between the two signals is determined more accurately. This effected with a counter (55, 56) whose count is applied to the phase comparator (7) to determine the digits after the decimal point for the phase difference. Furthermore, a controller (9) is provided in an automatic control system (7, 10, 8) for controlling the clock for the read counter (8), to which controller the output signal of the phase comparator (7), as well as information about the number of positive or negative bits to be stuffed during the next stuffing operation, is applied.

Claims

1. A circuit arrangement for adjusting the bit rates of two signals of which the signal having a higher bit rate (3) is structured in frames, wherein the circuit arrangement comprises a buffer memory (2), a write counter and a read counter (6, 8) as well as a phase comparator (7) and a control circuit (10) for inserting positive or negative stuff bits between bits of the lower bit rate signal (1), which is an input signal, comprising:

means for determining the least significant digits, namely the digits after the decimal point, of the phase difference between the write and read counters (6,

     8) and including an output of a further counter (55,

     56) being coupled to the phase comparator (7), the circuit arrangement comprising a clock means (53) for clocking the further counter (55,

     56) with a multiple of the bit clock of the lower bit rate signal; and

an automatic control system for controlling the clock for the read counter (8) and comprising a controller (9) which is coupled to the output of the phase comparator (7), an input of the control circuit (10) being coupled to the output of the controller (9) and the controller being coupled to an output of the control circuit (10) for receiving information about the number of positive or negative bits to be stuffed at a next stuffing operation.

2. A circuit arrangement as claimed in claim 1, characterized in that the controller (9) comprises an accumulator whose summing element (91) is arranged for summing the output signal of the phase comparator (7) and the number of positive or negative bits to be stuffed.