Method and apparatus for clock recovery in digital communication systems

• US 5,276,712 A
• Filed: 11/16/1989
• Issued: 01/04/1994
• Est. Priority Date: 11/16/1989
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Pearson, Jonathan D.
• Primary Examiner(s): Kuntz, Curtis
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US07/438,749
• Time in Patent Office: 1,510 Days
• Field of Search: 375/120, 375/106, 375/110, 375/118, 375/4, 331/1 R, 331/3, 328/72-74, 307/231, 307/518, 307/510
• US Class Current: 375/360
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A technique for recovering a clock from a digitally encoded communication signal uses a low-Q resonator and limiter for generating a coarse clock signal comprising a series of rectangular pulses at a frequency substantially equal to the clock (though subject to phase jitter), and a filter circuit, such as a phase-locked-loop ("PLL"), preferably employing a Sequential Phase/Frequency Detector, to reduce the jitter superimposed on the coarse clock signal, so as to yield a well-behaved clock signal. By using a Sequential Phase/Frequency Detector, acquisition-aid circuitry generally is not required for the PLL.

Claims

1. Apparatus for recovering a clock signal from a digitally encoded data signal, said digitally encoded data signal representing a plurality of first and second digital states, each said digital state being defined within one of a plurality of bit intervals, a first plurality of said bit intervals having an associated transition between said first and second digital states, and a second plurality of bit intervals lacking an associated transition between said first and second digital states, said apparatus comprising:

A. pulse-supplying means for receiving said digitally encoded data signal and generating a coarse clock signal having a plurality of pulses each corresponding to one of said first plurality and second plurality of bit intervals, said pulses having a signal frequency substantially equal to the clock signal of the digitally encoded data signal, said pulse-supplying means having

a resonator for generating, from said digitally encoded data signal, a sinusoidal signal having a frequency substantially equal to said clock signal to said digitally encoded data signal,

and a limiter for receiving said sinusoidal signal and converting said sinusoidal signal to a coarse clock signal by producing a series of unipolar rectangular pulses having a frequency controlled by said resonator frequency;

B. a phase-locked loop circuit coupled to receive as an input said coarse clock signal from said pulse-supplying means for reducing phase jitter superimposed thereon, and producing an output signal in the form of a clock signal having a generally well-behaved clock signal recovered from the digitally encoded data signal, said phase-locked-loop circuit having

an oscillator operating at an oscillator frequency controlled by an input signal, said oscillator capable of being controlled to operate at said signal frequency;

a sequential phase detector, operating at a detector frequency, said sequential phase detector having a first input and a second input, said sequential phase detector having an output comprising said oscillator input signal for controlling said oscillator to adjust said oscillator frequency;

a first digital frequency scaler, coupled between said limiter and said first input of said sequential phase detector, receiving said series of unipolar rectangular pulses, said first digital frequency scaler dividing said signal frequency of said series of unipolar rectangular pulses by a selected number greater than the number 1 giving said detector frequency;

and a second digital frequency scaler coupled between said oscillator and said second input of the sequential phase detector, said second digital frequency scaler dividing said oscillator output signal frequency by said selected number giving said detector frequency;

said sequential phase detector controlling said oscillator to adjust said oscillator frequency to match said signal frequency, and an output of said oscillator providing said clock signal.

2. The apparatus in accordance with claim 1, further comprising an input interface having

means for receiving an NRZ signal comprising a transition detector, said transition detector producing a series of pulses, each of said pulses representing a transition at a boundary between a 1 bit and a 0 bit of said NRZ signal;

means for receiving a biopolar RZ signal comprising a full-wave rectifier, said full-wave rectifier producing a unipolar RZ signal;

means for receiving a unipolar RZ signal;

and means for supplying a selected one of said series of pulses from said transition detector, said bipolar RZ, and said unipolar RZ as said digitally encoded data signal to said pulse-supplying means.

3. An apparatus for reducing jitter in a coarse clock signal from a digitally encoded data signal comprising:

first means for providing a digitally encoded data signal having a pulse corresponding to each transition of said input signal through an input interface having a transition detector to process an NRZ signal and a full-wave rectifier to process a bipolar RZ signal;

means coupled to said first means for receiving said digitally encoded data signal, comprising a resonator producing a sinusoidal signal having a frequency substantially equal that of said digitally encoded data signal;

means for receiving said sinusoidal signal comprising a limiter and converting said sinusoidal signal to a series of unipolar rectangular pulses at a first input frequency to produce a coarse clock signal;

means for receiving said series of unipolar rectangular pulses comprising a phase-locked-loop, said phase-locked-loop having an oscillator and a sequential phase detector, sequential phase detector being associated with first and second scalers, one of said scalers disposed at each of two inputs thereof, said first scaler receiving said series of unipolar rectangular pulses and dividing said first input frequency thereof by a selected number greater than the number 1, said oscillator responsive to an output signal from said sequential phase detector to produce an output signal at a second input frequency, said second scaler dividing said second input frequency by a selected second number greater than the number 1, said divided frequencies from said first and second scalers controlling said sequential phase detector, said oscillator producing a clock signal with reduced jitter from said oscillator output signal.

4. An apparatus for reducing jitter in a coarse clock signal from a digitally encoded data signal comprising:

an input interface having means for receiving an NRZ signal, means for receiving a bipolar RZ signal, means for receiving a unipolar RZ signal, and means for supplying a selected one of said NRZ, bipolar RZ and unipolar RZ as said digitally encoded data signal;

a pulse-supplying means for receiving said digitally encoded data signal and generating a coarse clock signal, said pulse-supplying means having a resonator and a limiter;

and a phase-locked-loop circuit coupled to receive as an input said coarse signal from said pulse-supplying means and producing a generally well-behaved clock signal with reduced phase jitter.