Real time adaptive probabilistic neural network system and method for data sorting

• US 5,276,772 A
• Filed: 01/31/1991
• Issued: 01/04/1994
• Est. Priority Date: 01/31/1991
• Status: Expired due to Term

• Current Assignee: Exelis Incorporated (L3Harris Technologies, Inc.)
• Original Assignee: AIL Systems, Inc. (L3Harris Technologies, Inc.)
• Inventors: Thompson, James, Wang, C. David
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): Downs, Robert W.
• Application Number:
  US07/648,194
• Time in Patent Office: 1,069 Days
• Field of Search: 395/27, 395/21, 395/22, 395/23, 395/24, 364/517, 342/197
• US Class Current: 706/20
• CPC Class Codes: G01J 3/453 by correlation of the amplitudes
• CPC Class Codes: G01S 13/24 using frequency agility of carrier wave
• CPC Class Codes: G01S 13/348 using square or rectangular modulation, e.g. diplex radar for ranging over short distances
• CPC Class Codes: G01S 13/726 Multiple target tracking
• CPC Class Codes: G01S 13/931 of land vehicles
• CPC Class Codes: G01S 17/95 for meteorological use
• CPC Class Codes: G01S 7/021 Auxiliary means for detecting or identifying radar signals or the like, e.g. radar jamming signals
• CPC Class Codes: G01S 7/2883 using FFT processing
• CPC Class Codes: G01S 7/417 involving the use of neural networks
• CPC Class Codes: G06F 18/2414 Smoothing the distance, e.g. radial basis function networks [RBFN]
• CPC Class Codes: G06N 3/047 Probabilistic or stochastic networks
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: Y02A 90/10 Information and communication technologies [ICT] supporting adaptation to climate change, e.g. for weather forecasting or climate simulation

Abstract

An adaptive probabilistic neural network (APNN) includes a cluster processor circuit which generates a signal which represents a probability density function estimation value which is used to sort input pulse parameter data signals based upon a probability of obtaining a correct match with a group of input pulse parameter data signals that have already been sorted. In the APNN system, a pulse buffer memory circuit is contained within the cluster processor circuit and temporarily stores the assigned input pulse parameter data signals. The pulse buffer memory circuit is initially empty. As the input pulse parameter data signals are presented to the APNN, the system sorts the incoming data signals based on the probability density function estimation value signal generated by each currently operating cluster processor circuit. The current input pulse parameter data signal is sorted and stored in the pulse buffer memory circuit of the cluster processor circuit. A small probability density function estimation value signal indicates the current unassigned input pulse parameter data signal is not recognized by the APNN system. A large probability density function estimation value signal indicates a match and the current input pulse parameter data signal will be included within a particular cluster processor circuit.

Claims

1. A real time data sorting adaptive probabilistic neural network system comprising:

(a) a plurality of cluster processor circuits, each cluster processor circuit generating an output signal representing a probability density function estimation value, each cluster processor circuit including;

(1) a pulse buffer memory circuit, the pulse buffer memory circuit having a plurality of serially connected registers for storing input pulse parameter data signals assigned to a respective cluster processor circuit;

(2) a plurality of processing elements, each of the processing elements being coupled to a corresponding register of the pulse buffer memory circuit for receiving assigned input pulse parameter data signals stored in the pulse buffer memory circuit, each of the processing elements further receiving current unassigned input pulse parameter data signals, each processing element providing an output signal;

(3) a plurality of exponential function circuits, each of the exponential function circuits being coupled to a corresponding processing element, each exponential function circuit performing an exponential function on the output signal of each processing element and providing an output signal in response thereto; and

(4) a summation circuit coupled to each of the exponential function circuits of the respective cluster processor circuit, the summation circuit receiving the output signals from the exponential function circuits and performing an addition function thereon and providing an output signal representing a probability density function estimating value;

(b) a decision logic circuit, the decision logic circuit being coupled to the summation circuit of each cluster processor circuit, the decision logic circuit comparing the output signal of each summation circuit of the corresponding cluster processor circuit with at least a first threshold value signal, and providing a decision address signal in response thereto,

(c) a switching circuit, the switching circuit being coupled to the decision logic circuit and to each of the cluster processor circuits and further receiving current unassigned input pulse parameter data signals and assigning the current unassigned input pulse parameter data signals to a respective cluster processor circuit for storage in the pulse buffer memory circuit of the respective cluster processor circuit in response to the decision address signal from the decision logic circuit; and

a storage register circuit, the storage register circuit being coupled to the switching circuit, the switching circuit providing the current unassigned input pulse parameter data signal to the storage register circuit when the output signal of the summation circuit of each cluster processor circuit is less than the threshold value signal and greater than a second threshold value signal.

2. A system as defined by claim 1, wherein the switching circuit is coupled to the pulse buffer memory circuit of each cluster processor circuit, the switching circuit assigning the current unassigned input pulse parameter data signal to the pulse buffer memory circuit of a currently operating cluster processor circuit if the summation circuit output signal representing a probability density function estimation value of the currently operating cluster processor circuit is at least equal to a first threshold value signal, and wherein the switching circuit assigns the current unassigned input pulse parameter data signal to the pulse buffer memory circuit of a newly operating cluster processor which was previously a non-operating cluster processor if the summation circuit output signal representing the probability density function estimation value of each currently operating cluster processor circuit is less than the first threshold value.

3. A method of sorting input pulse parameter data signals which comprises the steps of:

(a) inputting a current unassigned input pulse parameter data signal into at least one of a plurality of processing elements contained within a plurality of currently operating cluster processor circuits;

(b) generating a first signal representing a probability density function estimation value in response to the input pulse parameter data signals of each currently operating cluster processor circuit of the plurality of cluster processors, the probability density function estimation value signal being generated using the current unassigned input pulse parameter data signal and using a plurality of assigned input pulse parameter data signals stored in a pulse buffer memory circuit of each currently operating cluster processor circuit;

(c) comparing the first signal representing the probability density function estimation value generated by each currently operating cluster processor circuit to at least a first threshold value signal in a decision logic circuit;

(d) generating a decision address signal in response to the comparison of the first signal and the first threshold value signal, the decision address signal being provided to a switching circuit, the decision address signal denoting a currently operating cluster processor circuit when the first signal representing the probability density function estimation value is at least equal to the first threshold value signal, the decision address signal denoting and activating a non-operating cluster processor circuit when the first signal representing the probability density function estimation value is at most equal to the first threshold value signal;

(e) assigning the current unassigned input pulse parameter data signal from the switching circuit to the cluster processor circuit corresponding to the decision address signal provided to the switching circuit; and

(f) storing the current unassigned input pulse parameter data signal in the pulse buffer memory circuit of the cluster processor circuit according to the decision address signal received by the switching circuit.

4. A method as defined by claim 3, which includes the further steps of comparing the first signal representing a probability density function estimation value to a second threshold value signal in the decision logic circuit;

and denoting a storage register circuit and assigning the current unassigned input pulse parameter data from the switching circuit to the storage register circuit when the first signal, representing the probability density function estimation value, is less than the first threshold value and greater than the second threshold value signal.

5. A method as defined by claim 4, which includes the further step of manually setting the level of at least one of the first and second threshold value signals.

6. A method as defined by claim 4, wherein the first threshold value signal is greater in magnitude than the second threshold value signal.