Computer system having a selectable cache subsystem

• US 5,276,832 A
• Filed: 06/19/1990
• Issued: 01/04/1994
• Est. Priority Date: 06/19/1990
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Holman, Thomas H. Jr.
• Primary Examiner(s): RUDOLPH, REBECCA
• Application Number:
  US07/541,103
• Time in Patent Office: 1,295 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/425, 395/400, 361/397, 361/400, 365/63
• US Class Current: 711/3
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory

Abstract

A cache subsystem for a computer system which includes a cache memory and a cache control means. When the processor subsystem of the computer system requests data, information related to the location of the data within the memory subsystem of the computer is input to the cache subsystem. The control means receives an address bus bit field and transmits control signals which vary depending on the received address bus bit field to the cache memory to look for the requested data. The address bus bit field is configured based upon the dimensions of the cache memory and includes information as to where the data would be stored within the cache memory. As different cache memories are of different dimensions, means for modifying the address bus bit field generated by the cache control means based on the dimensions of the cache memory are provided so that the cache subsystem may be readily configured to operate with different sized cache memories.

Claims

1. A computer system which includes a processor subsystem, a memory subsystem, and a cache subsystem, said cache subsystem comprising:

a cache memory of specified dimensions coupled within said cache subsystem via slots, said slots capable of receiving an alternative cache memory of different specified dimensions;

cache memory control means for receiving an address bus bit field corresponding to a requested address from said processor subsystem and transmitting control signals to said cache memory based on said received address bus bit field, said address bus bit field providing an address within said cache memory corresponding to said address requested by said processor subsystem;

means for modifying said address bus bit field based on said dimensions of said cache memory; and

means for addressing said cache memory via said modified address bus bit field;

wherein said address bus bit field is comprised of a tag address field, a set address field and a line select field, and wherein said means for modifying said address bus bit field based on said dimensions of said cache memory further comprises means for modifying said line select address field, said tag address field and said set address field; and

wherein said means for means for modifying said address bus bit field based on said dimensions of said cache memory further comprises means for providing a duplicate of a portion of said set address field within said tag field.

2. The computer system as set forth in claim 1 wherein said cache memory control means for transmitting control signals to said cache memory further comprises:

a cache controller for receiving inputs corresponding to said tag address field, said set address field and said line select address field from said processor subsystem, said cache controller generating address signals to said cache memory indicative of the tag address of said tag address field.

3. A computer system as set forth in claim 2 further comprising:

address latching means for receiving inputs corresponding to said set address location field and said line select address field from said processor subsystem, said address latching means generating address signals to said cache memory indicative of the set address and line select address of said requested address.

4. A computer system as set forth in claim 3 wherein said cache controller generates at least one control signal for enabling said address latching means.

5. A computer system as set forth in claim 4 wherein said cache controller generates at least one control signal enabling said cache memory to transmit data to said processor subsystem.

6. A computer system as set forth in claim 3 wherein said cache memory comprises sixteen 4K×

4 static Random Access Memories (RAM) and said address bus bit field further comprises an eighteen bit tag address field, a nine bit set address location field and a one bit line select address field.

7. A computer system as set forth in claim 3 wherein said cache memory comprises sixteen 16K×

4 static RAMs and said address bus bit field further comprises an eighteen bit tag address field, a nine bit set address location field and a three bit line select address field.

8. A computer system as set forth in claim 7 wherein said cache memory eighteen bit tag address field further comprise sixteen tag address bits and two set address bits for double checking said set address.

9. A computer system as set forth in claim 8 wherein said address latching means is comprised of a pair of address latches, said cache memory is comprised of a series of static RAM chips and wherein said cache subsystem further comprises:

a printed circuit board having a first group of sockets for mounting said cache controller, a second group of sockets for mounting said address latches and a third group of sockets for mounting said series of static RAM chips.

10. A computer system as set forth in claim 9 further comprising:

a series of jumper connectors, one for each of said series of static RAM chips;

said third group of sockets is further comprised of 24 pin receiving sockets for each one of said series of static RAM chips; and

said cache memory is comprised of sixteen 22 pin 4K×

4 static RAMs, each of said pins configured to be received in one of said sockets, each of said jumper connectors permitting an associated 22 pin static RAM to operate in a 24 pin receiving socket.

11. A computer system as set forth in claim 3 wherein said cache memory is comprised of a series of static RAM chips, each of said static RAM chips having a series of inputs identically connected to said address latching means and wherein said cache subsystem further comprises:

a first three way jumper for alternately connecting a first one of said inputs of each of said series of static RAM chips to either a first output of said address latching means transmitting a first one of said address signals generated by said address latching means or a second output of said address latching means transmitting a second one of said address signals generated by said address latching means; and

a second three way jumper for alternately connecting a second one of said inputs of each of said series of static RAM chips to either a third output of said address latching means transmitting a third one of said address signals generated by said address latching means or a fourth output of said address latching means transmitting a fourth one of said address signals generated by said address latching means.

12. A computer system as set forth in claim 3 further comprising:

means for generating a snoop address bus bit field; and

means for modifying said snoop address bus bit field based on said dimensions of said cache memory.

13. A computer system as set forth in claim 3 wherein said cache controller further comprises:

a first series of address terminals, each of said first series of address terminals connected to one of said tag address field inputs;

a second series of address terminals;

a third series of address terminals;

a first three-way jumper connector for alternately connecting a first one of said third series of address terminals to a first one of said line address field inputs or to ground;

a second three-way jumper connector for alternately connecting a second one of said third series of address terminals to a second one of said line address field inputs or to ground; and

each remaining one of said third series of address terminals being connected to one of said line address field inputs.

14. A computer system as set forth in claim 13, further comprising:

a third three-way jumper connector for alternately connecting a first one of said second series of address terminals to a first one of said set address field inputs or to a second one of said set address field inputs;

a fourth three-way jumper connector for alternately connecting a second one of said second series of address terminals to a third one of said set location field inputs or to a fourth one of said set address field inputs; and

wherein each remaining one of said second series of address terminals is connected to one of said set address field inputs.

15. A computer system as set forth in claim 14 wherein when said first one of said second series of address terminals is connected to said second one of said set location field inputs and said second one of said second series of address terminals is connected to said fourth one of said set address field inputs, two of said first series of address terminals are connected to two of said set address field inputs.

16. A computer system as set forth in claim 14 wherein said cache memory is comprised of a series of static RAM chips, each of said static RAM chips having a series of inputs identically connected to said address latching means and wherein said cache subsystem further comprises:

a fifth three way jumper for alternately connecting a first one of said inputs of each of said series of static RAM chips to either a first output of said address latching means transmitting a first one of said address signals generated by said address latching means or a second output of said address latching means transmitting a second one of said address signals generated by said address latching means; and

a sixth three way jumper for alternately connecting a second one of said inputs of each of said series of static RAM chips to either a third output of said address latching means transmitting a third one of said address signals generated by said address latching means or a fourth output of said address latching means transmitting a fourth one of said address signals generated by said address latching means.

17. A cache subsystem having a selectable cache memory, comprising:

a printed circuit board;

means for installing a selectable one of a first removable cache memory of a first size and a second removable cache memory of a second size on said printed circuit board;

a cache controller installed on said printed circuit board for receiving a series of signals corresponding to an address within said cache memory installed on said printed circuit board and generating control signals to said cache memory installed on said printed circuit board based upon said series of received address signals;

means for modifying said series of address signals based on said size of said cache memory installed on said printed circuit board; and

means for addressing said installed cache memory via said modified address bus bit field;

wherein either said first removable cache memory or said second removable cache memory is installed on said printed circuit board and said address signal modifying means adjusts the number and order of said series of address signals transmitted to said cache controller based upon the size of said installed cache memory;

wherein said first removable cache memory is comprised of a plurality of 4K×

4 static RAM chips and said second removable cache memory is comprised of a plurality of 16K×

4 static RAM chips;

wherein said printed circuit board further comprising a series of groups of sockets, each said group of sockets either receiving one of said static RAMs of said first cache memory or one of said static RAMs of said second cache memory; and

wherein said static RAMs of said first cache memory have a first number of connector pins and said static RAMs of said second cache memory have a second number of connector pins different from said first number of pins; and

wherein said cache subsystem further comprises jumper connector means for permitting both said static RAMs of said first cache memory and said static RAMs of said second cache memory to operate in groups of sockets which correspond to said large number of static RAM pins.

18. A cache subsystem as set forth in claim 17 wherein said series of address signals is comprised of first, second and third fields, said first field indicative of a tag address, said second field indicative of a set address and said third field indicative of a line select address and wherein said address signal modifying means generates a three bit line select address field when said second removable cache is installed and said address signal modifying means generates a one bit line select address field when said first removable cache memory is installed.

19. A cache subsystem as set forth in claim 18 wherein said address signal modifying means further comprises means for grounding two of said three address signal bits which comprise said three bit line select address field when said first removable cache memory is installed.

20. A cache subsystem as set forth in claim 17 wherein said series of address signals is comprised of first, second and third fields, said first field indicative of a tag address, said second field indicative of a set address and said third field indicative of a line select address and wherein said address signal modifying means generates a one bit line select address field, a nine bit set address field and an eighteen bit tag address field when said first cache memory is installed and wherein said address signal modifying means further comprises means for switching two of said set address bits into said line select address field and duplicating two of said tag address bits in said set address field when said first cache memory is removed and said second cache memory is installed.

21. A cache subsystem as set forth in claim 20 wherein said cache controller also receives a second series of signals corresponding to a snoop address and wherein said cache subsystem further comprises means for modifying said series of snoop address signals based on said size of said cache memory installed on said printed circuit board.

22. A cache subsystem as set forth in claim 21 wherein said series of snoop address signals is comprised of first, second and third fields, said first field indicative of a snoop tag address, said second field indicative of a snoop set address and said third field indicative of a snoop line select address and wherein said snoop address signal modifying means generates a one bit snoop line select address field, a nine bit snoop address set address field and an eighteen bit snoop tag address field when said first cache memory is installed and wherein said snoop address signal modifying means further comprises means for switching two of said snoop set address bits into said snoop line select address field and duplicating two of said snoop tag address bits in said snoop set address field when said first cache memory is removed and said second cache memory is installed.

23. A cache subsystem as set forth in claim 20 further comprising:

address latching means for receiving inputs corresponding to said set address field and said line select address field and transmitting address latch signals to said installed cache memory, each of said static RAM chips comprising said installed cache memory having a series of inputs connected to said address latching means;

means for connecting a first one of said inputs of each of said series of static RAM chips to either a first output of said address latching means transmitting a first one or a second output of said address latching means transmitting a second one of said address signals generated by said address latching means; and

means for connecting a second one of said inputs of each of said series of static RAM chips to either a third output of said address latching means transmitting a third one or a fourth output of said address latching means transmitting a fourth one of said address signals generated by said address latching means;

wherein said first static RAM inputs are connected to said first output and said second static RAM inputs are connected to said third output when said first cache memory is installed and said first static RAM inputs are connected to said second output and said second static RAM inputs are connected to said fourth output when said second cache memory is installed.

24. A cache subsystem having a selectable 32 Kbyte or 128 Kbyte cache memory, comprising:

a printed circuit board;

a 32 Kbyte cache memory;

a 128 Kbyte cache memory;

means for selectively installing said 32 Kbyte cache memory or said 128 Kbyte cache memory on said printed circuit board;

a cache controller installed on said printed circuit board and configured for receiving a 31 bit address signal corresponding to an address within said installed cache memory and generating control signals to said installed cache memory based upon said received address signal; and

means for generating said 31 bit address signal as an eighteen bit tag address, nine bit set address, and one bit line select address signal when said 32 Kbyte cache memory is installed and generating said 31 bit address signal as an eighteen bit tag address, nine bit set address, and three bit line select address signal when said 128 Kbyte cache memory is installed.

25. A cache subsystem as set forth in claim 24 wherein said means for generating said 24 bit address signal when said 128 Kbyte cache memory is installed produces an address signal having an eighteen bit tag address field filled with sixteen tag address bits and two set address bits, a nine bit set address field filled with nine set bits, two of which duplicate said two set bits in said tag address field and a three bit line select address filled with three line select address bits.

26. A cache subsystem as set forth in claim 25 further comprising means for generating a 31 bit snoop address signal as an eighteen bit tag address, nine bit set address, and one bit line select address signal when said 32 Kbyte cache memory is installed and generating said 31 bit snoop address signal as an eighteen bit tag address, nine bit set address, and three bit line select address signal when said 128 Kbyte cache memory is installed.

27. A cache subsystem as set forth in claim 26 wherein said means for generating said 31 bit snoop address signal when said 128 Kbyte cache memory is installed produces a snoop address signal having an eighteen bit tag address field filled with sixteen tag address bits and two set address bits, a nine bit set address field filled with nine set location bits, two of which duplicate said two set address bits in said tag address field and a three bit line select address field filled with three line select bits.