Fast access memory structure

• US 5,276,846 A
• Filed: 01/30/1992
• Issued: 01/04/1994
• Est. Priority Date: 09/15/1986
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Busch, Robert E., Bachman, Bruce E., Redman, Theodore M., Thoma, Endre P., Aichelmann, Frederick J. Jr.
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): Elmore, Reba I.
• Application Number:
  US07/829,608
• Time in Patent Office: 705 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/400 MS File, 395/425 MS File
• US Class Current: 711/165
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A memory chip, comprising a chip memory section organized to hold a plurality of separate blocks of data, with each of the data blocks containing M individual data units; a circuit for addressing a given block of data in the chip memory section; and an N data unit chip parallel output interface from the memory chip where N is less than M, and N is greater than one. The memory chip further comprises a chip register for receiving from the chip memory section at least a portion of an addressed block of data, which portion comprises P data units, where P is greater than N, the chip register having P register stages for holding the P data units of the addressed data block, wherein the P register stages are grouped into at least a first and second groups of stages, with no group of stages comprising more than N register stages and with at least one of the groups of register stages having a plurality of stages. The memory chip also includes a gating structure for gating the respective groups of stages to the N data unit parallel output interface, the gating structure including at least a first gate circuit for gating in parallel the data units held in the first group of stages to the N data unit parallel output interface in accordance with a TOGGLE logic signal, and a second gate circuit for gating in parallel the data units held in the second group of stages to the N data unit parallel output interface in accordance with a NOT TOGGLE logic signal.

Claims

1. A random access memory chip, comprising:

a chip memory organized to hold a plurality of separate blocks of data, with each of said data blocks containing M individual data units in contiguous groups of N data units, where M is greater than N, and N is greater than one, with each data bit unit having its own unique address within said blocks, said memory having a predetermined wrap protocol, wherein said wrap protocol is a prescribed order for calling for all of said M data units in a given data block starting with a designated target data unit address and proceeding in said prescribed order, wherein a data unit at the end of a data block is contiguous in said prescribed order with a data unit at the beginning of said data block so that said beginning data unit follows said end data unit in said data block;

means for randomly addressing a data unit within a given block of data by means of a designated target address;

an N data unit chip output parallel interface from said memory;

chip register means for holding a given block of data, said chip register means having at least M register stages for holding said M data units of said given data block, wherein said M register stages are grouped into at least a first and a second contiguous groups of N stages each, said chip register means including first gating means for gating said first stage group of N register stages to said N data unit output parallel interface, followed in sequence, by said second stage group and higher groups, said first gating means comprising a first register gate for receiving and gating in parallel said first group of N stages to said N data unit output interface in accordance with a TOGGLE logic signal, and a second register gate for receiving and gating in parallel said second group of N stages to said N data unit output interface in accordance with a NOT TOGGLE logic signal; and

chip steering means for providing in a first set, and in any desired order, the data unit at said target address along with N-1 data units having following contiguous addresses for said memory wrap protocol from within said data block to said first group of N register stages, and for providing each successive set of N data units with following contiguous addresses in said wrap protocol to said second and higher register stage groups, wherein the data unit, if any, following the end data unit in the data block for the wrap protocol is always the beginning data unit in the data block; and

further including means for preventing said chip steering means from steering upon the occurrence of a NOT STEERING logic signal.

2. A random access memory chip, comprising:

a chip memory organized to hold a plurality of separate blocks of data, with each of said data blocks containing M individual data bits in an initial order in contiguous groups of N bits, where M is greater than N, and N is greater than one, with each data bit having its own unique address within said blocks, said memory having a predetermined wrap protocol wherein said wrap protocol is a prescribed order calling for said M bits to be accessed starting with a target bit address and proceeding in said block is contiguous in said prescribed order with a bit at the beginning of said data block so that said beginning bit follows said end bit in said data block;

chip address means for randomly addressing a data bit in a given block of data held in said chip memory by means of a target address;

an N bit chip output parallel interface from said chip memory;

means for holding said given data block in its initial data bit order within said chip;

means for reordering said data bit order into a reordered data bit order so that the bit with the target address along with N-1 bits having following contiguous addresses in said memory wrap protocol are held in any order in the first N positions in said reordered data bit order, and reordering so that each successive set of N bits with following contiguous addresses in said wrap protocol is held in second and higher N position groups, respectively, within said reordered data bit order, wherein the bit, if any, following the end bit in the data block is always the beginning bit in the data block; and

first chip gating means for gating said first N positions in said reordered data bit order to said N bit chip output parallel interface, followed, in sequence, by said second N positions and higher N position groups, said first chip gating means comprising a first register gate for receiving and gating in parallel said first N positions to said N bit chip output parallel interface in accordance with a TOGGLE logic signal, and a second register gate for receiving and gating in parallel said second N positions to said N bit chip output parallel interface in accordance with a NOT TOGGLE logic signal; and

further comprising means for preventing said reordering means from performing bit reordering, said preventing means operating upon the occurrence of a NOT STEERING logic signal.

3. A memory chip, comprising:

a chip memory section organized to hold a plurality of separate blocks of data, with each of said data blocks containing M individual data units;

means for addressing a data unit within a given block of data in said chip memory section;

an N data unit chip parallel output interface from said memory chip, where N is less than M, and N is greater than one;

chip register means for receiving from said chip memory section at least a portion of an addressed block of data, which portion comprises P data units, where P is greater than N, said chip register means having P register stages for holding said P data units of said addressed data block, wherein said P register stages are grouped into at least a first and second group of stages, with no group of stages comprising more than N register stages and with at least one of said groups of register stages having a plurality of stages; and

gating means for gating said respective groups of stages to said N data unit parallel output interface, said gating means including at least a first gate circuit for gating in parallel the data units held in said first group of stages to said N data unit parallel output interface in accordance with a TOGGLE logic signal, and a second gate circuit for gating in parallel the data units held in said second group of stages to said N data unit parallel output interface in accordance with a NOT TOGGLE logic signal.

4. A memory chip as defined in claim 3, wherein said chip memory section comprises a random access memory.

5. A memory chip as defined in claim 3, wherein said chip memory section is organized so that M is equal to an integer multiple of N.

6. A memory chip as defined in claim 3, wherein P in said chip register means is equal to M.

7. A memory chip as defined in claim 3, wherein each of said first and second groups of stages has N register stages therein.

8. A memory chip as defined in claim 3, wherein said chip memory section is organized so that each data unit in said blocks of data has its own unique address, said chip memory section further being organized so that said M individual data units in said block of data are in groups of N data units, said chip memory section yet further being organized to have a predetermined wrap protocol, wherein said wrap protocol is prescribed order for calling for all of said M data units in a given data block starting with an N data unit group containing a designated target data unit address and proceeding in said prescribed order, wherein a data unit at the end of a data block is contiguous in said prescribed order with a data unit at the beginning of said data block so that said beginning data unit follows said end data unit in said data block;

and

wherein said addressing means comprises means for randomly addressing one of said data units within a given block of data by means of said target data unit address.

9. A memory chip, comprising:

a chip memory section organized to hold a plurality of separate blocks of data, with each of said blocks of data containing M individual data units organized into at least a first and a second groups of N data units each, where M is greater than N and N is greater than one, with each data unit having its own unique address within its respective data block, said chip memory section having a predetermined wrap protocol, wherein said wrap protocol is a prescribed order for calling for all of said M data units in a given data block starting with the one of said first or second N data unit groups containing a designated target data unit address and proceeding in said prescribed order, wherein a data unit at the end of a data block is contiguous in said prescribed order with a data unit at the beginning of said data block so that said beginning data unit follows said end data unit in said data block;

a circuit for randomly addressing one of said data units within a given block of data in said chip memory section by means of said target data unit address;

an N data unit chip parallel output interface from said memory chip;

a chip register for receiving from said chip memory section a given block of data containing said target data unit, said chip register having at least M register stages for holding said M data units of said given block of data, wherein said M register stages are grouped into a first and second groups of N stages each; and

a gating circuit for gating in parallel the data units held in said first group of N stages to said N data unit parallel output interface in accordance with a TOGGLE logic signal, and for gating in parallel the data units held in said second group of N stages to said N data unit parallel output interface in accordance with a NOT TOGGLE logic signal.