Automatic writeback and storage limit in a high-performance frame buffer and cache memory system

• US 5,276,851 A
• Filed: 11/06/1992
• Issued: 01/04/1994
• Est. Priority Date: 12/22/1989
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Conroy, David G., Thacker, Charles P.
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): Nguyen, Hiep T.
• Application Number:
  US07/972,885
• Time in Patent Office: 424 Days
• US Class Current: 711/120
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)

Abstract

A computer system includes a plurality of central processing units (CPUs) each of which has a direct napped cache memory. The system also includes a main memory, and one or more display frame buffers. The cache normally operates in a write back mode, whereby updated data is written back to main memory only when a cache block is reallocated to store a new block of data. A tag for each block of data stored in the cache includes a Shared flag which indicates whether the corresponding block of data may be stored in the cache of another CPU. When a block of data stored is modified, it is immediately written to main memory if the tag for that block has an enabled Shared flag. To make the cache operate in a write-through mode for blocks of image data, the system stores an enabled Shared flag in the cache whenever a block of frame buffer data is stored in the cache. A circuit in the cache detects when the CPU is writing an entire block of image data to an address in the frame buffer and causes the cache to write the block of image data directly to the frame buffer without storing the image data in the cache. An address circuit in the cache stores image data from the frame buffer only in a predefined fraction of the cache, and thereby restricts the amount of other data stored in the cache which may be displaced by image data.

Claims

1. In a computer system having a multiplicity of processors, a main memory coupled to said processors by a memory bus, said main memory storing data at specified addresses within a predefined address space, said predefined address space being at least partially shared by said multiplicity of processors;

said memory bus carrying signals which denote addresses to which data is being stored by said processors;

said main memory including at least one frame buffer for storing image data at addresses in a predefined portion of said address space, and other memory for storing additional data in portions of said address space other than said predefined portion;

display means for displaying image data stored in said at least one frame buffer;

a plurality of cache means coupled to said memory bus, each cache means coupled to one of said processors for providing said processor with access to portions of said address space at higher speed than said main memory, each said cache means including a direct mapped cache array for storing blocks of data and tag means for denoting what portion of said address space is stored in each of said blocks;

said tag means including a tag for each said block of data stored in said cache means, said tag denoting an address value, and a shared flag that is enabled when said block of data may be stored in another one of said cache means;

each cache means including cache logic means for automatically writing a block of data stored in said cache means to said main memory whenever said block of data is modified by said processor and said tag for said block has an enabled shared flag;

said cache logic means furthermore including means for writing to said main memory blocks of data stored in said cache means that have been modified by said processor and that have a disabled shared flag in said tag for said block only when said blocks of data are displaced from said cache means;

said cache logic means including means for asserting a shared signal on said memory bus whenever any of said multiplicity of processors, other than said processor coupled to said cache means, accesses data that is also stored in said cache means; and

each cache means including shared flag logic means for storing an enabled shared flag in said cache means (A) whenever a block of image data from said at least one frame buffer is stored in said cache means, regardless of whether said block of image data may be stored in another one of said cache means, and (B) whenever a block of data is stored in said cache memory means, said block of data having an address in the portion of said address space corresponding to said other memory, and a shared signal present on said memory bus indicates that said block of data stored may also be stored in another one of said cache means;

wherein said shared flag logic means stores a disabled status flag in said cache means whenever a block of data having an address in the portion of said address space corresponding to said other memory is stored in said cache means and no shared signal is present on said memory bus;

whereby said cache means always writes modified blocks of image data to said at least one frame buffer, and writes modified data, shared with other ones of said cache means and having an address in the portion of said address space corresponding to said other memory, to said other memory.

2. In a computer system as set forth in claim 1, said cache logic means including block writing means for detecting when said processor coupled to said cache means is writing a block of image data to said at least one frame buffer and for writing said block of image data directly to said at least one frame buffer without storing said block of image data in said cache array.

3. In a computer system as set forth in claim 1, said cache logic means including address circuit means for storing blocks of image data from said at least one frame buffer only in a predefined portion of said cache array, said predefined portion comprising no more than one half of said cache array;

whereby said cache logic means restricts the amount of other data stored in said cache which may be displaced by image data from said at least one frame buffer.

4. In a computer system as set forth in claim 3, wherein said tags for said predefined portion of said cache array each include means for denoting an address value indicative of a portion of said at least one frame buffer which is stored in the corresponding block of data in said cache array.

5. In a computer system having a multiplicity of processors, a main memory coupled to said processors by a memory bus, said main memory storing data at specified addresses within a predefined address space, said memory bus including an address bus carrying address signals, said predefined address space being at least partially shared by said multiplicity of processors;

said main memory including at least one frame buffer for storing image data at addresses in a predefined portion of said address space, and other memory for storing additional data in portions of said address space other than said predefined portion;

display means for displaying image data stored in said at least one frame buffer;

a plurality of cache means coupled to said memory bus, each cache means coupled to one of said processors for providing said processor with access to portions of said address space at higher speed than said main memory, each said cache means including a direct mapped cache array for storing blocks of data and tag means for denoting what portion of said address space is stored in each of said blocks;

said tag means including a tag for each said block of data stored in said cache means;

each cache means including cache logic means for storing blocks of image data from said at least one frame buffer only in a predefined portion of said cache array, said predefined portion comprising no more than one half of said cache array;

said cache logic means including address logic coupled to said memory bus for generating a cache array address corresponding to a subset of the address signals on said address bus, said address logic including circuitry that replaces at least one predefined bit of said cache array address with a predefined value whenever said memory bus is carrying image data having an address in said predefined portion of said address space, thereby restricting storage of image data in said cache array to cache array addresses with said at least one predefined bit set to said predefined value;

whereby said cache logic means restricts the amount of other data stored in said cache which may be displaced by image data from said at least one frame buffer.

6. In a computer system as set forth in claim 5, said at least one predefined bit of said cache array address including at least one most significant bit of said cache array address.

7. In a computer system as set forth in claim 5, said cache logic means including block writing means for detecting when said processor coupled to said cache means is writing a block of image data to said at least one frame buffer and for writing said block of image data directly to said at least one frame buffer without storing said block of image data in said cache array.

8. In a computer system as set forth in claim 7, wherein said at least one predefined bit of said cache array address including at least one most significant bit of said cache array address.

9. In a computer system having a processor, a main memory coupled to said processor by a memory bus, said main memory storing data at specified addresses within a predefined address space, said memory bus carrying signals which denote addresses to which data is being stored by said processor;

said main memory including at least one frame buffer for storing image data at addresses in a predefined portion of said address space, and other memory for storing additional data in portions of said address space other than said predefined portion;

display means for displaying image data stored in said at least one frame buffer;

cache means coupled to said memory bus and said processor for providing said processor with access to portions of said address space at higher speed than said main memory, said cache means including a direct mapped cache array for storing blocks of data and tag means for denoting what portion of said address space is stored in each of said blocks;

said tag means including a tag for each said block of data stored in said cache means, said tag denoting an address value, and a status flag; and

said cache means including status logic means for storing an enabled status flag in said cache means whenever a block of image data from said at least one frame buffer is stored in said cache means;

wherein said status logic means stores a disabled status flag in said cache means whenever a block of data having an address in the portion of said address space corresponding to said other memory is stored in said cache means, unless said block of data is also stored in another cache means coupled to another processor;

each cache means including cache logic means for automatically writing a block of data stored in said cache means to said main memory whenever said block of data is modified by said processor and said status tag for said block is enabled;

said cache logic means furthermore including means for writing to said main memory blocks of data stored in said cache means that have been modified by said processor and that have a disabled status flag in said tag for said block only when said blocks of data are displaced from said cache means;

whereby said cache means always writes modified blocks of image data to said at least one frame buffer.

10. In a computer system as set forth in claim 9, said cache logic means including block writing means for detecting when said processor is writing a block of image data to said at least one frame buffer and for writing said block of image data directly to said at least one frame buffer without storing said block of image data in said cache array.

11. In a computer system as set forth in claim 9, said cache logic means including address circuit means for storing blocks of image data from said at least one frame buffer only in a predefined portion of said cache array, said predefined portion comprising no more than one half of said cache array;

whereby said cache logic means restricts the amount of other data stored in said cache which may be displaced by image data from said at least one frame buffer.

12. In a computer system having a processor, a main memory coupled to said processor by a memory bus, said main memory storing data at specified addresses within a predefined address space, said memory bus including an address bus carrying address signals that denote addresses to which data is being stored and addresses from which data is being retrieved by said processor;

said main memory including at least one frame buffer for storing image data at addresses in a predefined portion of said address space, and other memory for storing additional data in portions of said address space other than said predefined portion;

display means for displaying image data stored in said at least one frame buffer;

cache means coupled to said memory bus and said processor for providing said processor with access to portions of said address space at higher speed than said main memory, said cache means including a direct mapped cache array for storing blocks of data and tag means for denoting what portion of said address space is stored in each of said blocks;

said tag means including a tag for each said block of data stored in said cache means;

said cache means including cache logic means for storing blocks of image data from said at least one frame buffer only in a predefined portion of said cache array, said predefined portion comprising no more than one half of said cache array;

said cache logic means including address logic coupled to said memory bus for generating a cache array address corresponding to a subset of the address signals on said address bus, said address logic including means for replacing at least one predefined bit of said cache array address with a predefined value whenever said memory bus is carrying image data having an address in said predefined portion of said address space, thereby restricting storage of image data in said cache array to cache array addresses with said at least one predefined bit set to said predefined value;

whereby said cache logic means restricts the amount of other data stored in said cache which may be displaced by image data from said at least one frame buffer.

13. The computer system set forth in claim 12, wherein said at least one predefined bit of said cache array address includes at least one most significant bit of said cache array address.

14. In a computer system as set forth in claim 12, said cache logic means including block writing means for detecting when said processor coupled to said cache means is writing a block of image data to said at least one frame buffer and for writing said block of image data directly to said at least one frame buffer without storing said block of image data in said cache array.

15. The computer system set forth in claim 14, wherein said at least one predefined bit of said cache array address includes at least one most significant bit of said cache array address.

16. In a computer system having a processor, a main memory coupled to said processor by a memory bus, said main memory storing data at specified addresses within a predefined address space, said memory bus including an address bus carrying address signals that denote addresses to which data is being stored and addresses from which data is being retrieved by said processor;

said main memory including at least one frame buffer for storing image data at addresses in a predefined portion of said address space, and other memory for storing additional data in portions of said address space other than said predefined portion;

display means for displaying image data stored in said at least one frame buffer;

cache means coupled to said memory bus and said processor for providing said processor with access to portions of said address space at higher speed than said main memory, said cache means including a direct mapped cache array for storing blocks of data and tag means for denoting what portion of said address space is stored in each of said blocks;

said tag means including a tag for each said block of data stored in said cache means;

said cache means including cache logic means for storing blocks of image data from said at least one frame buffer only in a predefined portion of said cache array, said predefined portion comprising no more than one half of said cache array;

said cache logic means including address logic coupled to said memory bus for generating a cache array address corresponding to a subset of the address signals on said address bus, said address logic including means for replacing a plurality of predefined bits of said cache array address with a predefined value whenever said memory bus is carrying image data having an address in said predefined portion of said address space, thereby restricting storage of image data in said cache array to cache array addresses with said plurality of predefined bits set to said predefined value;

whereby said cache logic means restricts the amount of other data stored in said cache which may be displaced by image data from said at least one frame buffer.

17. The computer system set forth in claim 16, wherein said plurality of predefined bits of said cache array address includes a plurality of most significant bits of said cache array address.

18. In a computer system as set forth in claim 16, said cache logic means including block writing means for detecting when said processor coupled to said cache means is writing a block of image data to said at least one frame buffer and for writing said block of image data directly to said at least one frame buffer without storing said block of image data in said cache array.

19. The computer system set forth in claim 18, wherein said plurality of predefined bits of said cache array address includes a plurality of most significant bits of said cache array address.

20. In a computer system having a multiplicity of processors, a main memory coupled to said processors by a memory bus, said main memory storing data at specified addresses within a predefined address space, said memory bus including an address bus carrying address signals, said predefined address space being at least partially shared by said multiplicity of processors;

said main memory including at least one frame buffer for storing image data at addresses in a predefined portion of said address space, and other memory for storing additional data in portions of said address space other than said predefined portion;

display means for displaying image data stored in said at least one frame buffer;

a plurality of cache means coupled to said memory bus, each cache means coupled to one of said processors for providing said processor with access to portions of said address space at higher speed than said main memory, each said cache means including a direct mapped cache array for storing blocks of data and tag means for denoting what portion of said address space is stored in each of said blocks;

said tag means including a tag for each said block of data stored in said cache means;

each cache means including cache logic means for storing blocks of image data from said at least one frame buffer only in a predefined portion of said cache array, said predefined portion comprising no more than one half of said cache array;

said cache logic means including address logic coupled to said memory bus for generating a cache array address corresponding to a subset of the address signals on said address bus, said address logic including means for replacing a plurality of predefined bits of said cache array address with a predefined value whenever said memory bus is carrying image data having an address in said predefined portion of said address space, thereby restricting storage of image data in said cache array to cache array addresses with said plurality of predefined bits set to said predefined value;

whereby said cache logic means restricts the amount of other data stored in said cache which may be displaced by image data from said at least one frame buffer.

21. In a computer system as set forth in claim 20, said plurality of predefined bits of said cache array address including a plurality of most significant bits of said cache array address.

22. In a computer system as set forth in claim 20, said cache logic means including block writing means for detecting when said processor coupled to said cache means is writing a block of image data to said at least one frame buffer and for writing said block of image data directly to said frame buffer without storing said block of image data in said cache array.

23. In a computer system as set forth in claim 22, said plurality of predefined bits of said cache array address including a plurality of most significant bits of said cache array address.