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Automatic writeback and storage limit in a high-performance frame buffer and cache memory system

  • US 5,276,851 A
  • Filed: 11/06/1992
  • Issued: 01/04/1994
  • Est. Priority Date: 12/22/1989
  • Status: Expired due to Term
First Claim
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1. In a computer system having a multiplicity of processors, a main memory coupled to said processors by a memory bus, said main memory storing data at specified addresses within a predefined address space, said predefined address space being at least partially shared by said multiplicity of processors;

  • said memory bus carrying signals which denote addresses to which data is being stored by said processors;

    said main memory including at least one frame buffer for storing image data at addresses in a predefined portion of said address space, and other memory for storing additional data in portions of said address space other than said predefined portion;

    display means for displaying image data stored in said at least one frame buffer;

    a plurality of cache means coupled to said memory bus, each cache means coupled to one of said processors for providing said processor with access to portions of said address space at higher speed than said main memory, each said cache means including a direct mapped cache array for storing blocks of data and tag means for denoting what portion of said address space is stored in each of said blocks;

    said tag means including a tag for each said block of data stored in said cache means, said tag denoting an address value, and a shared flag that is enabled when said block of data may be stored in another one of said cache means;

    each cache means including cache logic means for automatically writing a block of data stored in said cache means to said main memory whenever said block of data is modified by said processor and said tag for said block has an enabled shared flag;

    said cache logic means furthermore including means for writing to said main memory blocks of data stored in said cache means that have been modified by said processor and that have a disabled shared flag in said tag for said block only when said blocks of data are displaced from said cache means;

    said cache logic means including means for asserting a shared signal on said memory bus whenever any of said multiplicity of processors, other than said processor coupled to said cache means, accesses data that is also stored in said cache means; and

    each cache means including shared flag logic means for storing an enabled shared flag in said cache means (A) whenever a block of image data from said at least one frame buffer is stored in said cache means, regardless of whether said block of image data may be stored in another one of said cache means, and (B) whenever a block of data is stored in said cache memory means, said block of data having an address in the portion of said address space corresponding to said other memory, and a shared signal present on said memory bus indicates that said block of data stored may also be stored in another one of said cache means;

    wherein said shared flag logic means stores a disabled status flag in said cache means whenever a block of data having an address in the portion of said address space corresponding to said other memory is stored in said cache means and no shared signal is present on said memory bus;

    whereby said cache means always writes modified blocks of image data to said at least one frame buffer, and writes modified data, shared with other ones of said cache means and having an address in the portion of said address space corresponding to said other memory, to said other memory.

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