Hardware semaphores in a multi-processor environment

• US 5,276,886 A
• Filed: 10/11/1990
• Issued: 01/04/1994
• Est. Priority Date: 10/11/1990
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Chips and Technologies, Inc. (Intel Corporation)
• Inventors: Dror, Asael
• Primary Examiner(s): CHUN, DEBRA
• Application Number:
  US07/596,101
• Time in Patent Office: 1,181 Days
• Field of Search: 395/325, 395/725, 395/650
• US Class Current: 710/240
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

In a computer system having at least two processors, each processor having an associated memory, the processors being coupled to one another through an interface unit by means of a bus, hardware semaphores to regulate access to shared resources are disclosed. Each semaphore is one bit wide and can be written to obtain the desired state. When reading the semaphore, if the contents is a one, then a one is returned. If the content is zero, a zero is returned but the semaphore is automatically reset to one.

Claims

1. In a multiprocessor computer system having at lest two processors, each processing having an associated memory and each processor being coupled to the other through an interface unit, the processors also sharing a resource, interface apparatus for maintaining and signaling an accessibility status of said shared resource, said interface apparatus comprising:

a hardware semaphore for said shared resource, the semaphore being one bit wide;

hardware circuitry means for detecting when one of said processors attempts to write a value to the semaphore and for forcing the semaphore to said written value regardless of any previous value of the semaphore;

hardware circuitry means for detecting when one of said processors attempts to read the semaphore, and for determining a status of the semaphore; and

hardware circuitry means, coupled to said detecting and determining means, for returning a zero value and simultaneously resetting the semaphore to a one if the status is a zero, and for returning a one value if the status is a one, wherein a returned value of zero indicates that the shared resource is accessible.

2. A method for controlling synchronization between processors in a multi-processor system, the system having at least two processors, each processor having an associated memory and each processor being coupled to the other through an interface unit having a hardware semaphore means, the method comprising the steps of:

initiating a first write access with a value of one to the semaphore means by one of said processors;

in response to said first write access, forcing the semaphore means to a value of one regardless of any previous value of the semaphore;

signalling an event in one of said processors by initiating a second write access with a value of zero by said processor to the semaphore means;

in response to said second write access, forcing the semaphore means to a value of zero; and

reading a synchronization value from the semaphore means by one of said processors to determine if an event has occurred, the value of the semaphore means remaining a one if said synchronization value was a one and the value of the semaphore means changing to one automatically if said synchronization value was a zero.

3. The method of claim 2, wherein said multiprocessor system comprises more than two processors, wherein each of said processors access said semaphore means to maintain synchronization.

4. A method for maintaining and signaling accessibility status for resources such as input/output devices and counters in a multi-processor system, the system having at least two processors, each processor having an associated memory and each processor being coupled to the other through an interface unit having a hardware semaphore means for a shared resource, the method comprising the steps of:

initiating a first write access with a value of one by one of said processors to the semaphore means;

in response to said first write access, forcing the semaphore means to a value of one regardless of any previous value of the semaphore;

initiating a second write access with a value of zero by one of said processors to the semaphore means;

in response to said second write access, forcing the semaphore means to a value of zero;

initiating a read access of the semaphore means by one of said processors; and

in response to said read access of the semaphore means, returning a status equal to a value of the semaphore means and automatically changing the value of the semaphore means to a one if the status is a zero, the semaphore means value remaining unchanged if the status is a one, a returned status equal to zero indicating that the resource associated with the semaphore means can be accessed.