Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure

• US 5,278,438 A
• Filed: 12/19/1991
• Issued: 01/11/1994
• Est. Priority Date: 12/19/1991
• Status: Expired due to Term

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Inventors: Kim, Manjin J., Young, Jein-Chen
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LIMANEK, ROBERT P
• Application Number:
  US07/810,250
• Time in Patent Office: 754 Days
• Field of Search: 357/23.5, 357/55, 357/23.9, 357/23.3, 357/91, 357/23.6 G, 257/316, 257/397, 257/398, 257/618, 365/185
• US Class Current: 257/316
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile storage device is provided with at least one stacked poly gate structure formed on the substrate and disposed between a first trench and a second trench. The trenches each having two walls. A first doped area having a first conductivity type extending along the wall of the first trench and a second doped area having a second conductivity type extending along the wall of the second trench. The first doped area and the second doped area having heights greater than widths, the heights being parallel to the trench walls and the widths being perpendicular thereto. The trench walls are lined with a metal silicide to decrease resistivity.

Claims

1. A nonvolatile storage device comprising:

a substrate;

at least a first trench and a second trench extending partially into the substrate, each trench having at least one vertical wall;

at least one stacked poly-dielectric gate structure formed on the substrate and disposed between the trenches, the gate structure having a first side and a second side;

a first spacer disposed on the first side of the gate structure and a second spacer disposed on the second side of the gate structure;

a first doped area of a first conductivity type under the first spacer and formed along at least part of a wall of the first trench;

a second doped area of a first conductivity type under the second spacer and formed along at least part of a wall of the second trench; and

the first doped area and the second doped area having heights greater than widths, the heights being measured parallel to the trench walls and the widths being measured perpendicular thereto.

2. The device of claim 1, further comprising a conductive silicide formed in the first doped area and the second doped area covering at least part doped areas formed along the trench walls.

3. The device of claim 1, further comprising a third doped area traversing the bottom of each trench, the third doped area having a second conductivity type which is an opposite conductivity type from the first conductivity type.

4. The device of claim 1, wherein the device further comprises a single metallization layer extending across a top surface of the substrate above the gate structure for making contact to the gate structure.

5. The device of claim 1, wherein at least one trench further comprises

a second wall separated from the first wall by a bottom;

and

a third doped area extending along the second wall of the trench.

6. A nonvolatile storage device comprising:

a substrate;

a plurality of parallel trenches extending partially through the substrate;

each trench having a first sidewall and a second sidewall and at least a first doped area traversing one sidewall of the trench without a conductive layer electrically coupling the first sidewall and the second sidewall, each sidewall defining one bitline;

an array of rows and columns of stacked poly gate structures formed on the substrate, each column separating two of the trenches;

the doped areas having heights greater than widths, the heights being parallel to the trench sidewalls and the widths being perpendicular thereto.

7. The device of claim 6, further comprising

a second doped area extending along a second wall of each trench;

and

the second doped areas having heights greater than widths, the heights being parallel to the trench walls and the widths being perpendicular thereto.

8. The device of claim 6, further comprising a conductive silicide formed in the doped areas in regions traversing the trench walls.

9. The device of claim 7, further comprising a third doped area traversing the bottom of each trench and the third doped area having a conductivity type different from the other doped areas.

10. The device of claim 6, wherein the device further comprises a single metallization layer extending across a top surface of the substrate.

11. The device of claim 6, wherein the doped area along one trench wall is common to a column of stacked poly gate structures.

12. A nonvolatile storage device comprising:

a substrate;

at least a first trench and a second trench extending partially into the substrate, each trench having at least one wall;

at least one stacked poly-dielectric gate structure formed on the substrate and disposed between the trenches, the gate structure having a first side and a second side;

a first spacer disposed on the first side of the gate structure and a second spacer disposed on the second side of the gate structure;

a first doped area of a first conductivity type under the first spacer and formed at least partially within and along at least part of a wall of the first trench;

a second doped area of a first conductivity type under the second spacer and formed at least partially within and along at least part of a wall of the second trench;

the first doped area and the second doped area having heights greater than widths, the heights being measured parallel to the trench sidewalls and the widths being measured perpendicular thereto.