Threshold crossover detector with improved digital noise rejection
First Claim
1. A zero crossover detector for sensing an analog input signal and for producing a digital output signal at the exact moment that the analog input signal crosses through zero voltage, comprisingfirst means for sensing an analog input signal and operative intermittently to generate a first binary output signal each time said input signal exceeds a predetermined voltage while going in one direction,second means for sensing said analog input signal and operative intermittently to generate a second binary output signal each time said input signal exceeds a predetermined voltage while going in the opposite direction,third means for sensing said analog input signal and operative for each cycle thereof to generate a third binary signal coincident with a zero voltage crossover of said input signal, andmeans connected to said sensing means and responsive to each generation of said third binary signal to produce a digital output signal coincident with said zero crossover of said input signal, provided that each of said first and second binary signals is generated in a cycle of said input signal preceding generation of said third binary signal.
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Accused Products
Abstract
The detector applies an analog input signal through respectively positive and negative offset voltages to the inputs of two comparators, one of which produces a first output signal as the input signal passes beyond a predetermined minimum voltage in the positive going direction, and the other of which produces a second output signal when the input voltage exceeds a minimum predetermined value in a negative going direction. The input signal is also applied directly to the input of a third comparator the output of which produces a third signal each time the input signal crosses over zero voltage in a positive going direction. The first and second comparator output signals are applied to the reset and set terminals, respectively, of a first flip flop. The output of this first flip flop, and the output of the third comparator are applied through an AND gate to the set terminal of a second flip flop. The second flip flop produces at its output a digital signal precisely at the time that a signal is produced at the output of the third comparator, provided the outputs of the first and second comparators have been successively generated in the cycle of the input voltage immediately preceding the output signal of the third comparator.
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Citations
13 Claims
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1. A zero crossover detector for sensing an analog input signal and for producing a digital output signal at the exact moment that the analog input signal crosses through zero voltage, comprising
first means for sensing an analog input signal and operative intermittently to generate a first binary output signal each time said input signal exceeds a predetermined voltage while going in one direction, second means for sensing said analog input signal and operative intermittently to generate a second binary output signal each time said input signal exceeds a predetermined voltage while going in the opposite direction, third means for sensing said analog input signal and operative for each cycle thereof to generate a third binary signal coincident with a zero voltage crossover of said input signal, and means connected to said sensing means and responsive to each generation of said third binary signal to produce a digital output signal coincident with said zero crossover of said input signal, provided that each of said first and second binary signals is generated in a cycle of said input signal preceding generation of said third binary signal.
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11. A method of sensing an analog input signal and for producing a substantially noise free digital output signal at the exact moment that the analog input signal crosses through zero voltage, comprising
sensing an analog input signal, generating a first binary signal after said input signal has exceeded a first predetermined minimum voltage in a positive going direction during each cycle thereof, generating a second binary signal after said input signal has exceeded a second predetermined minimum voltage in a negative going direction during each cycle thereof, generating a third binary signal at the end of each cycle of said input voltage at the moment that the input voltage passes through zero in a positive going direction, momentarily generating a fourth binary signal upon successive generation of said first and second binary signals in a given cycle of said input signal, and generating a digital output signal concurrently with said third binary signal each time said third binary signal is generated in the presence of said fourth binary signal.
Specification