Buffered feedthrough crossbar switch
First Claim
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1. An N×
- M crossbar switch, where N and M are positive integers comprising;
N data inputs, N data input buffers, N buffered data outputs, M feedthrough inputs, M data outputs, and an array of M multiplexers, each multiplexer having N matrix inputs;
each of said data inputs being connected to one of said input buffers, each of said input buffers having an output connected to one of said matrix inputs to each of said multiplexers;
each of said input buffers having a separate output connected to one and only one of said buffered data outputs;
each of said data inputs being addressably connected through said multiplexer array to each of said data outputs; and
each of said feedthrough inputs being addressably connected to one and only one of said data outputs, said crossbar switch further comprising;
M OR-gates, each OR-gate having a first input and a second input;
the output of each of said multiplexers being connected to the first input of one of said OR-gates;
each of said feedthrough inputs being connected to the second input of one of said OR-gates; and
the output of each of said OR-gates being connected to one of said data outputs.
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Abstract
An improved crossbar switch in which internal buffering is performed for input signals across the chip and in which an extra input for each output channel of the crossbar switch element is provided.
25 Citations
2 Claims
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1. An N×
- M crossbar switch, where N and M are positive integers comprising;
N data inputs, N data input buffers, N buffered data outputs, M feedthrough inputs, M data outputs, and an array of M multiplexers, each multiplexer having N matrix inputs; each of said data inputs being connected to one of said input buffers, each of said input buffers having an output connected to one of said matrix inputs to each of said multiplexers; each of said input buffers having a separate output connected to one and only one of said buffered data outputs; each of said data inputs being addressably connected through said multiplexer array to each of said data outputs; and each of said feedthrough inputs being addressably connected to one and only one of said data outputs, said crossbar switch further comprising; M OR-gates, each OR-gate having a first input and a second input; the output of each of said multiplexers being connected to the first input of one of said OR-gates; each of said feedthrough inputs being connected to the second input of one of said OR-gates; and the output of each of said OR-gates being connected to one of said data outputs. - View Dependent Claims (2)
- M crossbar switch, where N and M are positive integers comprising;
Specification
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Current Assigneethe united states of america as represented by the secretary of the navy
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Original Assigneethe united states of america as represented by the secretary of the navy
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InventorsHaber, William J.
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Primary Examiner(s)Chin, Wellington
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Assistant Examiner(s)Kizou, Hassan
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Application NumberUS07/685,588Time in Patent Office1,006 DaysField of Search370/53, 370/56, 370/57, 370/58.1-58.3, 370/59-60, 370/63-65, 370/65.5, 370/66-68, 370/112, 340/825.79, 340/825.8, 340/825.83, 340/825.85, 340/825.89, 340/825.9, 340/825.91, 379/242, 379/271, 379/291-292, 379/306, 379/333, 379/335US Class Current370/380CPC Class CodesH04J 2203/0005 Switching elementsH04J 2203/0012 Switching modules and their...H04J 3/08 Intermediate station arrang...H04Q 11/04 for time-division multiplex...H04Q 11/0478 Provisions for broadband co...
