DMD architecture and timing for use in a pulse width modulated display system

• US 5,278,652 A
• Filed: 03/23/1993
• Issued: 01/11/1994
• Est. Priority Date: 04/01/1991
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sampsell, Jeffrey B., Urbanus, Paul M.
• Primary Examiner(s): Powell, Mark R.
• Application Number:
  US08/035,525
• Time in Patent Office: 294 Days
• Field of Search: 340/793, 340/799, 340/784.31, 340/784 E, 340/784 R, 365/230.03, 365/230.01, 365/230.06, 358/230, 358/231, 358/160, 358/233
• US Class Current: 348/571
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2352/00 Parallel handling of streams of display data
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2037 with specific control of sub-frames corresponding to the least significant bits
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: H04N 2005/7466 Control circuits therefor
• CPC Class Codes: H04N 3/08 having a moving reflector
• CPC Class Codes: H04N 3/127 using liquid crystals
• CPC Class Codes: H04N 5/7458 the modulator being an array of deformable mirrors, e.g. digital micromirror device [DMD]
• CPC Class Codes: H04N 9/30 using solid-state colour display devices

Abstract

It is possible to replace a standard tuning unit in a television with spatial light modulator circuitry to improve the resolution seen by the viewer. The invention herein provides a system architecture, individual parts of the system, and techniques for minimizing the burst data rate while maintaining a reasonable system speed. The resultant system provides better resolution with a manageable data rate and bandwidth.

Claims

1. A method of displaying data comprising addressing the contents of memory cells and loading said contents onto display pixels wherein data from an alternate data path is loaded onto said pixels instead of the contents of said memory calls, said data causing all pixels in said row to display the same state.

2. A method of displaying data comprising addressing the contents of memory cells and loading said contents onto display pixels wherein said loading step includes the use of a decoder to address rows of said pixels simultaneously said decoder having additional inputs wherein activation of said inputs causes said decoder to address groups of said rows simultaneously wherein one or more groups may be addressed simultaneously.