Method and apparatus for partially overmolded integrated circuit package

• US 5,278,726 A
• Filed: 01/22/1992
• Issued: 01/11/1994
• Est. Priority Date: 01/22/1992
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bernardoni, Lonnie L., Swirbel, Thomas J., Arledge, John K.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): WHANG, YOUNG
• Application Number:
  US07/824,136
• Time in Patent Office: 720 Days
• Field of Search: 361/395, 361/397, 361/400, 361/401, 361/402, 361/403, 361/411, 361/417, 361/418, 228/180.2, 257/778, 257/782, 257/787, 257/789, 257/666, 257/670, 257/673, 174/52.2, 174/259
• US Class Current: 361/783
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A partially overmolded integrated circuit package (10) comprises a substrate (14) having circuit traces (11) and a semiconductor die receiving area (15) for attachment of a semiconductor die to the semiconductor die receiving area. Conductive bumps (18) are then applied to a plurality of contact pads on the semiconductor die. Then overmolding compound (16) is applied over the semiconductor die and a portion of the conductive bumps, leaving a portion of the conductive bumps partially exposed (19). Finally, interconnections (13) between the exposed portion of the conductive bumps and the circuit traces of the substrate are formed.

Claims

1. A method for forming a partially overmolded integrated circuit package, comprising the steps of:

(a) providing a substrate having conductive circuit runners;

(b) attaching a semiconductor die having contact pads to the substrate;

(c) applying conductive bumps to the contact pads of the semiconductor die;

(d) transfer molding a resin over the semiconductor die and a first lower portion of each conductive bump, so as to leave a second upper portion of each conductive bump exposed and elevated above the uppermost surface of the transfer molded resin;

(e) electrically interconnecting the second upper portion of each conductive bump to the conductive circuit runners.

2. The method of claim 1, wherein said conductive bumps are comprised of gold.

3. The method of claim 1, wherein said transfer molded resin is a thermoset epoxy molding compound.

4. The method of claim 1, wherein said transfer molded resin has sloped sides to allow for photolithography.

5. The method of claim 1, wherein said conductive bumps are coupled to the circuit runners of the substrate using thin film photolithography.

6. The method of claim 1, wherein said method further comprises the step of flattening the conductive bump.

7. A partially overmolded integrated circuit package, comprising:

a substrate having circuit traces and a semiconductor die receiving area;

a semiconductor die having contact pads, for placement on the semiconductor die receiving area;

means for attaching the semiconductor die to the substrate;

conductive bumps applied to the contact pads of the semiconductor die;

transfer molded resin over the semiconductor die and a first lower portion of the conductive bumps, leaving a second upper portion of the conductive bumps partially exposed and elevated above the uppermost surface of the transfer molded resin;

interconnections between the second upper portion of the conductive bumps and the circuit traces of the substrate.

8. The package of claim 7, wherein said conductive bumps are comprised of gold.

9. The package of claim 7 wherein said overmolding compound comprises a thermoset epoxy molding compound.

10. The package of claim 7, wherein said transfer molded resin is formed to have sloped sides to allow for photolithography.

11. The package of claim 7, wherein said conductive bumps are coupled to the circuit traces of the substrate with thin film metallization.

12. The package of claim 7, wherein said conductive bumps are flattened.

13. A partially overmolded integrated circuit package, comprising:

a printed circuit board having conductive circuit traces and a semiconductor die receiving area;

a semiconductor die attached to the semiconductor die receiving area, said semiconductor die having contact pads;

conductive bumps applied to the contact pads of the semiconductor die;

transfer molded resin over the semiconductor die and a first lower portion of the conductive bumps, leaving a second upper portion of the conductive bumps partially exposed and elevated above the uppermost surface of the transfer molded resin, and the transfer molded resin not covering the substrate conductive circuit traces; and

thin film interconnections between the second upper portion of the conductive bumps and the substrate conductive circuit traces.

14. The package of claim 13, wherein said conductive bumps are comprised of gold.

15. The package of claim 13 wherein said transfer molded resin comprises a thermoset epoxy molding compound.

16. The package of claim 13, wherein said transfer molded resin is formed to have sloped sides to allow for photolithography.

17. The package of claim 13, wherein said conductive bumps are coupled to the circuit traces of the substrate with thin film metallization.

18. The package of claim 13, wherein said conductive bumps are flattened.