Digital signal processing system

• US 5,278,781 A
• Filed: 04/23/1993
• Issued: 01/11/1994
• Est. Priority Date: 11/12/1987
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Sakiyama, Shiro, Toyokura, Masaki, Aono, Kunitoshi, Maruyama, Masakatsu, Araki, Toshiyuki
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/051,273
• Time in Patent Office: 263 Days
• Field of Search: 364/725, 364/736, 364/728.01, 364/728.03, 364/724.12, 364/724.16, 364/750.5, 364/784
• US Class Current: 708/523
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 2207/3884 Pipelining
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

A digital signal processing system includes a plurality of multiplier/accumulators for executing a pipeline processing operation. Each of the plurality of multiplier/accumulators includes a multiplication part and an addition part. The multiplication parts includes N pipeline registers for storing N intermediate outputs of a multiplier. The addition part includes a Wallace tree transformation unit for transforming a sum of N+1 inputs into two transformation outputs, and an adder for adding the two transformation outputs. The N+1 inputs includes the N intermediate outputs from the multiplication part and the one addition output from the adder.

Claims

1. A digital signal processing system comprising:

a plurality of multiplier/accumulator means connected in parallel for executing a pipeline processing operation, each of said plurality of multiplier/accumulator means having a multiplication part and an addition part, said multiplication part and said addition part having operation times which are nearly equalized with each other;

said multiplication part comprising a multiplier for receiving first and second multiplication inputs and generating first and second intermediate outputs having a sum corresponding to a product of said first and second multiplication inputs and two pipeline registers for respectively storing said first and second intermediate outputs of said multiplier;

said addition part comprising a Wallace tree transformation means for transforming a sum of three inputs into two transformation outputs, an adder means for adding said two transformation outputs into one addition output, and an accumulator register for storing said one addition output, said three inputs including said two intermediate outputs stored in and received from said two pipeline registers and as one addition input an output from said accumulator register in one of said plurality of multiplier/accumulator means.

2. A digital processing system as recited in claim 1, further comprising:

a plurality of processor elements each comprising (a) first and second inputs, (b) first and second outputs, (c) a RAM having coefficients stored therein, (d) a respective one of said multiplier/accumulator means having as said first and second multiplication inputs said first input and a coefficient from said RAM and having as said one addition input an output of a multiplexer, (e) said multiplexer having as inputs said second input and an output of said accumulator register of said multiplier accumulator means having an output coupled to said first output, and (f) a buffer register having as an input said output of said accumulator register and having an output coupled to said second output;

an output multiplexer having as inputs said second output of each of said plurality of processor elements for selecting one of said second outputs of said plurality of processor elements;

an input port coupled to said first input of each of said plurality of processor elements;

said first output of a (m-1)th processor element being coupled to said second input of said mth processor element, m being a positive integer greater than 1;

said second input of a first processor element having input thereto a value 0; and

,

each of said multiplexers of said processor elements and said output multiplexer being controlled for one of a convolution operation and a matrix calculation.

3. A digital processing system as recited in claim 1, further comprising:

M processor elements each comprising (a) plural inputs, (b) first and second outputs, (c) a first multiplexer having as inputs said plural inputs, (d) a RAM having coefficients stored therein, (e) a respective one of said multiplier/accumulator means having as said first and second multiplication inputs an output of said first multiplexer and a coefficient from said RAM and as said one addition input an output of a second multiplexer, (f) said second multiplexer having as inputs one of said plural inputs and an output of said accumulator register of said multiplier/accumulator means having an output coupled to said first output, and (g) a buffer register having as an input and output of said accumulator register and having an output coupled to said second output, M being a positive integer greater than one;

an output multiplexer having as inputs said second outputs of each of said M processor elements for selecting one of said second outputs of said M processing elements;

plural input ports coupled to said plural inputs of said M processor elements;

said first output of a (m-1)th processor element being connected to said one of said plural inputs of a mth processor element, m being an integer wherein 2<

m<

M;

said one of said plural inputs of a first processor element having input thereto a value 0; and

each of said first and second multiplexers of said processor elements being controlled for one of a convolution operation and matrix calculation.

4. A multiplier/accumulator having a pipeline configuration for a data processing system comprising:

a multiplication part and an addition part, said multiplication part and said addition part having operation times which are nearly equalized with each other;

said multiplication part comprising a multiplier for receiving first and second multiplication inputs and generating first and second intermediate outputs having a sum corresponding to a product of said first and second multiplication inputs and two pipeline registers for respectively storing said first and second intermediate outputs of said multiplier;

said addition part comprising a Wallace tree transformation means for transforming a sum of three inputs into two transformation outputs, an adder means for adding said two transformation outputs into one addition output, and an accumulator register for storing said one addition output, said three inputs including said two intermediate outputs stored in and received from said two pipeline registers and as one addition input an output from said accumulator register.