Square root operation device
First Claim
Patent Images
1. A square root operation device to find a square root on a floating-point number input operand where a base of an exponent is 2, comprising:
- exponential constant subtracting means for removing a bias of the exponent of said floating-point number input operand,exponent shifting means for right-shifting an output of said exponential constant subtracting means one bit place,exponential constant adding means for adding the bias of the exponent to an output of said exponent shifting means,normalizing means for left-shifting, when a value of the exponent less the bias is odd, a mantissa in said floating-point number input operand one bit place in order to cause the value of the exponent less the bias to be even,table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in an output of said normalizing means as an address,residue holding means for holding a residue when the square root is found by sequentially iterating a fixed number of bits beginning from a high-order position and descending in a downward order,multiplying means for executing a multiplication by inputting the residue output from said residue holding means and the approximation of square root'"'"'s reciprocal output from said table information storing means, as a multiplicand and a multiplier respectively,merged square root value holding means for holding a merged square root value as a combination of individual partial square root values which are high-order positions in the resulting product output from said multiplying means at each iteration,inverting means for inverting the partial square root value output from said multiplying means at every bit,multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said multiplying means,residue shifting means for left-shifting the residue output from said residue holding means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value,(R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output by said residue shifting means after shifting, a multiplicand S output from said multiplicand generating means and a multiplier T output from said inverting means, respectively,a holding data switching multiplexer for selecting either the output of said normalizing means or an output of said (R+S×
T+T) operating means, as an input of said residue holding means,constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said multiplying means,a correcting multiplexer for selecting either the partial square root value output from said multiplying means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value,digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with the merged square root value output from said merged square root value holding means, andmerged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value.
2 Assignments
0 Petitions
Accused Products
Abstract
By taking a high-order position in an operand which is normalized in a two bit unit by means of and output from a normalizing circuit as an address, an approximation of square root'"'"'s reciprocal is indexed by means of a table information storing unit. By multiplying an output of a residue holding circuit which takes a 0th residue as a normalized operand by the approximation of square root'"'"'s reciprocal by using a multiplying circuit, a partial square root value is found. The individual partial square root values each having a overlapped bit at each iteration are merged with one another by means of a digit aligning circuit and an adder. A residue for a next step in iterative computation is found by subtracting a product of a merged square root value and a partial square root value from a residue by means of an inverting circuit, a multiplicand generator, a (R+S×T) operation unit.
25 Citations
30 Claims
-
1. A square root operation device to find a square root on a floating-point number input operand where a base of an exponent is 2, comprising:
-
exponential constant subtracting means for removing a bias of the exponent of said floating-point number input operand, exponent shifting means for right-shifting an output of said exponential constant subtracting means one bit place, exponential constant adding means for adding the bias of the exponent to an output of said exponent shifting means, normalizing means for left-shifting, when a value of the exponent less the bias is odd, a mantissa in said floating-point number input operand one bit place in order to cause the value of the exponent less the bias to be even, table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in an output of said normalizing means as an address, residue holding means for holding a residue when the square root is found by sequentially iterating a fixed number of bits beginning from a high-order position and descending in a downward order, multiplying means for executing a multiplication by inputting the residue output from said residue holding means and the approximation of square root'"'"'s reciprocal output from said table information storing means, as a multiplicand and a multiplier respectively, merged square root value holding means for holding a merged square root value as a combination of individual partial square root values which are high-order positions in the resulting product output from said multiplying means at each iteration, inverting means for inverting the partial square root value output from said multiplying means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said multiplying means, residue shifting means for left-shifting the residue output from said residue holding means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output by said residue shifting means after shifting, a multiplicand S output from said multiplicand generating means and a multiplier T output from said inverting means, respectively,a holding data switching multiplexer for selecting either the output of said normalizing means or an output of said (R+S×
T+T) operating means, as an input of said residue holding means,constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said multiplying means, a correcting multiplexer for selecting either the partial square root value output from said multiplying means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with the merged square root value output from said merged square root value holding means, and merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value. - View Dependent Claims (2)
-
-
3. A square root operation device to find a square root on a floating-point number input operand where a base of an exponent is 2, comprising:
-
exponential constant subtracting means for removing a bias of the exponent of said floating-point number input operand, exponent shifting means for right-shifting an output of said exponential constant subtracting means one bit place, exponential constant adding means for adding the bias of the exponent to an output of said exponent shifting means, normalizing means for left-shifting, when a value of the exponent less the bias is odd, a mantissa in said floating-point number input operand one bit place in order to cause the value of the exponent less the bias to be even, table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in an output of said normalizing means as an address, residue holding means for holding a residue when the square root is found by sequentially iterating a fixed number of bits beginning from a high-order position and descending in a downward order, partial square root value holding means for holding a partial square root value at each iteration, and merged square root value holding means for holding a merged square root value as a combination of the individual partial square root values at each iteration, residue shifting means for left-shifting the residue output from said residue holding means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value, inverting means for inverting the partial square root value output from said partial square root value holding means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said partial square root value holding means, a residue multiplexer for selecting either a constant 0 or a residue output by said residue shifting means after shifting, a multiplicand multiplexer for selecting either the residue output from said residue holding means or an output of said multiplicand generating means, a multiplier multiplexer for selecting either the approximation of square root'"'"'s reciprocal output from said table information storing means or an output of said inverting means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting an output R of said residue multiplexer, an output S of said multiplicand multiplexer, and an output T of said multiplier multiplexer, respectively,a holding data switching multiplexer for selecting either the output of said normalizing means or an output of said (R+S×
T+T) operating means, as an input of said residue holding means,constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said partial square root value holding means, a correcting multiplexer for selecting either the partial square root value output from said partial square root value holding means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with the merged square root value output from said merged square root value holding means, and merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value, wherein high-order positions in the output of said (R+S×
T+T) operating means are sequentially held in said partial square root value holding means, as the partial square root value. - View Dependent Claims (4)
-
-
5. A square root operation device to find a square root vector in the order of element on an input operand in the order of element of a vector comprising a floating-point number where a base of an exponent is 2, comprising:
-
a preprocessing unit for performing a preprocess on said input operand, a main unit provided with first through last main circuits the number of which corresponds to that of iterating processes for repeatedly finding a partial square root value until a bit length of a merged square root value as a combination of the individual partial square root values becomes greater than that of a target square root, and a post-processing unit for performing a post-process on an output of said main unit, said preprocessing unit comprising; an input register for holding said input operand, exponential constant subtracting means for removing a bias of the exponent form an exponent part in an output of said input register, exponent holding means for holding an output of said exponential constant subtracting means, normalizing means for left-shifting, when a value of the exponent less the bias is odd, a mantissa part in the output of said input register one bit place in order to cause the value of the exponent less the bias to be even, a normalized operand register for holding an output of said normalizing means, exponent shifting means for right-shifting an output of said exponent holding means one bit place, exponential constant adding means for adding the bias of the exponent to an output of said exponent shifting means, and table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in an output of said normalized operand register as an address, said first main circuit in said main unit comprising; exponent holding means, residue holding means and table output information holding means which are connected to said exponential constant adding means, said normalized operand register and said table information storing means in said preprocessing unit respectively, in order to synchronize pipeline operations, multiplying means for executing a multiplication by inputting an output of said residue holding means as a multiplicand and an output of said table output information holding means as a multiplier so as to output high-order positions in the resulting product as a partial square root value, partial square root value holding means for holding the partial square root value output from said multiplying means, residue shifting means for left-shifting a residue output from said residue holding means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value, inverting means for inverting the partial square root value output from said partial square root value holding means at every bit, multiplicand generating means for generating a multiplicand from the partial square root value output from said partial square root value holding means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output by said residue shifting means after shifting, a multiplicand S output from said multiplicand generating means and a multiplier T output from said inverting means, respectively,constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said partial square root value holding means, and a correcting multiplexer for selecting either the partial square root value output from said partial square root value holding means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, said second and subsequent main circuits in said main unit each comprising; exponent holding means, residue holding means, merged square root value holding means and table output information holding means in order to synchronize pipeline operations, multiplying means for executing a multiplication by inputting an output of said residue holding means as a multiplicand and an output of said table output information holding means as a multiplier so as to output high-order positions in the resulting product as a partial square root value, partial square root value holding means for holding the partial square root value output from said multiplying means, residue shifting means for left-shifting a residue output from said residue holding means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value, inverting means for inverting the partial square root value output from said partial square root value holding means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said partial square root value holding means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output by said residue shifting means after shifting, a multiplicand S output from said multiplicand generating means and a multiplier T output from said inverting means, respectively,constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said partial square root value holding means, a correcting multiplexer for selecting either the partial square root value output from said partial square root value holding means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with a merged square root value output from said merged square root value holding means, and merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value, wherein; in said second and subsequent main circuits, said exponent holding means is connected to said exponent holding means in the preceding main circuit, said residue holding means is connected to said (R+S×
T+T) operating means in the preceding main circuit, and said table output information holding means is connected to said table output information holding means in the preceding main circuit,in said second main circuit, said merged square root value holding means is connected to said correcting multiplexer in said first main circuit, and in said third and subsequent main circuit, said merged square root value holding means is connected to said merged square root value calculation adding means in the preceding main circuit, said post-processing unit comprising; exponent holding means and merged square root value holding means which are connected to said exponent holding means and said merged square root value holding means in said last main circuit of said main unit respectively, in order to synchronize pipeline operations. - View Dependent Claims (6)
-
-
7. A square root operation device to find a square root on a fixed-point number input operand, comprising:
-
normalizing shift count detecting means for finding a shift count when said fixed-point number input operand is bit-normalized in a two bit unit, normalizing means for left-shifting said fixed-point number input operand on the basis of the shift count output from said normalizing shift count detecting means, table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in an output of said normalizing means as an address, residue holding means for holding a residue when the square root is found by sequentially iterating a fixed number of bits beginning from a high-order position and descending in a downward order, multiplying means for executing a multiplication by inputting the residue output from said residue holding means and the approximation of square root'"'"'s reciprocal output from said table information storing means, as a multiplicand and a multiplier respectively, merged square root value holding means for holding a merged square root value as a combination of individual partial square root values which are high-order positions in the resulting product output from said multiplying means at each iteration, inverting means for inverting the partial square root value output from said multiplying means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said multiplying means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output from said residue holding means, a multiplicand S output from said multiplicand generating means and a multiplier T output from said inverting means, respectively,shifting means for left-shifting an output of said (R+S×
T+T) operating means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value,a holding data switching multiplexer for selecting either the output of said normalizing means or an output of said shifting means, as an input of said residue holding means, constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said multiplying means, a correcting multiplexer for selecting either the partial square root value output from said multiplying means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with the merged square root value output from said merged square root value holding means, merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value, digit adjustment shift count calculating means for calculating a shift count of right-shifting to be carried out to the merged square root value output from said merged square root value calculation adding means on the basis of an output of said normalizing shift count detecting means, in order to obtain a target square root, and digit adjusting means for outputting the target square root by right-shifting the merged square root value output from said merged square root value calculation adding means on the basis of the shift count output from said digit adjustment shift count calculating means. - View Dependent Claims (8, 9, 10)
-
-
11. A square root operation device to find a square root on a fixed-point number input operand, comprising:
-
normalizing shift count detecting means for finding a shift count when said fixed-point number input operand is bit-normalized in a two bit unit, normalizing means for left-shifting said fixed-point number input operand on the basis of the shift count output from said normalizing shift count detecting means, table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in an output of said normalizing means as an address, residue holding means for holding a residue when the square root is found by sequentially iterating a fixed number of bits beginning from a high-order position and descending in a downward order, partial square root value holding means for holding the partial square root value at each iteration, and merged square root value holding means for holding a merged square root value as a combination of the individual partial square root values at each iteration, inverting means for inverting the partial square root value output from said partial square root value holding means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said partial square root value holding means, a residue multiplexer for selecting either a constant 0 or the residue output from said residue holding means, a multiplicand multiplexer for selecting either the residue output from said residue holding means or an output of said multiplicand generating means, a multiplier multiplexer for selecting either the approximation of square root'"'"'s reciprocal output from said table information storing means or an output of said inverting means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting an output R of said residue multiplexer, an output S of said multiplicand multiplexer and an output T output from said multiplier multiplexer, respectively,shifting means for left-shifting an output of said (R+S×
T+T) operating means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value,a holding data switching multiplexer for selecting either the output of said normalizing means or an output of said shifting means, as an input of said residue holding means, constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said partial square root value holding means, a correcting multiplexer for selecting either the partial square root value output from said partial square root value holding means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with the merged square root value output from said merged square root value holding means, merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value, digit adjustment shift count calculating means for calculating a shift count of right-shifting to be carried out to the merged square root value output from said merged square root value calculation adding means on the basis of an output of said normalizing shift count detecting means, in order to obtain a target square root, and digit adjusting means for outputting the target square root by right-shifting the merged square root value output from said merged square root value calculation adding means on the basis of the shift count output from said digit adjustment shift count calculating means, wherein high-order positions in the output of said (R+S×
T+T) operating means are sequentially held in said partial square root value holding means, as the partial square root value. - View Dependent Claims (12, 13, 14)
-
-
15. A square root operation device to find a square root vector in the order of element on an input operand in the order of element of a vector comprising a fixed-point number, comprising:
-
a preprocessing unit for performing a preprocess on said input operand, a main unit provided with first through last main circuits the number of which corresponds to that of iterating processes for repeatedly finding a partial square root value until a bit length of a merged square root value as a combination of the individual partial square root values becomes greater than that of a target square root, and a post-processing unit for performing a post-process on an output of said main unit, said preprocessing unit comprising; an input register for holding said input operand, normalizing shift count detecting means for finding a shift count when an output of said input register is bit-normalized in a two bit unit, normalizing means for left-shifting the output of said input register on the basis of the shift count output from said normalizing shift count detecting means, normalized operand register for holding an output of said normalizing means, normalizing shift count holding means for holding an output of said normalizing shift count detecting means, table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in an output of said normalized operand register as an address, said first main circuit in said main unit comprising; residue holding means, table output information holding means and normalizing shift count holding means which are connected to said normalized operand register, said table information storing means and normalizing shift count holding means in said preprocessing unit respectively, in order to synchronize pipeline operations, multiplying means for executing a multiplication by inputting an output of said residue holding means as a multiplicand and an output of said table output information holding means as a multiplier so as to output high-order positions in the resulting product thus calculated as a partial square root value, partial square root value holding means for holding the partial square root value output from said multiplying means, inverting means for inverting the partial square root value output from said partial square root value holding means at every bit, multiplicand generating means for generating a multiplicand from the partial square root value output from said partial square root value holding means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output from said residue holding means, a multiplicand S output from said multiplicand generating means and a multiplier T output from said inverting means respectively,shifting means for left-shifting an output from said (R+S×
T+T) operating means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value,constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said partial square root value holding means, and a correcting multiplexer for selecting either the partial square root value output from said partial square root value holding means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, said second and subsequent main circuits in said main unit each comprising; residue holding means, merged square root value holding means, table output information holding means and normalizing shift count holding means in order to synchronize pipeline operations, multiplying means for executing a multiplication by inputting an output of said residue holding means as a multiplicand and an output of said table output information holding means as a multiplier so as to output high-order positions in the resulting product as a partial square root value, partial square root value holding means for holding the partial square root value output from said multiplying means, inverting means for inverting the partial square root value output from said partial square root value holding means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said partial square root value holding means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output from said residue holding means, a multiplicand S output from said multiplicand generating means and a multiplier T output from said inverting means, respectively,shifting means for left-shifting an output from said (R+S×
T+T) operating means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value,constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said partial square root value holding means, a correcting multiplexer for selecting either the partial square root value output from said partial square root value holding means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with a merged square root value output from said merged square root value holding means, and merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value, wherein; in said second and subsequent main circuits, said residue holding means is connected to the shifting means in the preceding main circuit, said table output information holding means is connected to said table output information holding means in the preceding main circuit and said normalizing shift count holding means is connected to said normalizing shift count holding means in the preceding main circuit, in said second main circuit, said merged square root value holding means is connected to said correcting multiplexer in said first main circuit, and in said third and subsequent main circuits, said merged square root value holding means is connected to said merged square root value calculation adding means in the preceding main circuits, said post-processing unit comprising; merged square root value holding means and normalizing shift count holding means which are connected to said merged square root value calculation adding means and said normalizing shift count holding means in said last main circuit in said main unit, respectively, digit adjustment shift count calculating means for calculating a shift count of right-shifting to be carried out to the merged square root value output from said merged square root value calculation adding means on the basis of an output of said normalizing shift count detecting means, in order to obtain a target square root, and digit adjusting means for outputting the target square root by left-shifting the merged square root value output from said merged square root value calculation adding means on the basis of the shift count output from said digit adjustment shift count calculating means. - View Dependent Claims (16)
-
-
17. A square root operation device to find a square root on a floating-point number input operand where a base of an exponent is 2, comprising:
-
exponential constant subtracting means for removing a bias of the exponent of said floating-point number input operand, exponent shifting means for right-shifting an output of said exponential constant subtraction means one bit place, exponential constant adding means for adding the bias of the exponent to an output of said exponent shifting means, normalizing means for left-shifting, when a value of the exponent less the bias is odd, a mantissa in said floating-point number input operand one bit place in order to cause the value of the exponent less the bias to be even, table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in an output of said normalizing means as an address, residue holding means for holding a residue when the square root is found by sequentially iterating a fixed number of bits beginning from a high-order position and descending in a downward order, multiplying means for executing a multiplication by inputting the residue output from said residue holding means and the approximation of square root'"'"'s reciprocal output from said table information storing means, as a multiplicand and a multiplier respectively, merged square root value holding means for holding a merged square root value as a combination of individual partial square root values which are high-order positions in the resulting product output from said multiplying means at each iteration, inverting means for inverting the partial square root value output from said multiplying means at each bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said multiplying means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output from said residue holding means, a multiplicand S output from said multiplicand generating means and a multiplier T output from said inverting means, respectively,operation result shifting means for left-shifting an output from said (R+S×
T+T) operating means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value,a holding data switching multiplexer for selecting either the output of said normalizing means or an output of said operation result shifting means, as an input of said residue holding means, constant subtracting means for subtracting 1 from a least significant bit of the partial square root value output from said multiplying means, a correcting multiplexer for selecting either the partial square root value output from said multiplying means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with the merged square root value output from said merged square root value holding means, and merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value. - View Dependent Claims (18)
-
-
19. A square root operation device to find a square root on a floating-point number input operand where a base of an exponent is 2, comprising:
-
exponential constant subtracting means for removing a bias of the exponent of said floating-point number input operand, exponent shifting means for right-shifting an output of said exponential constant subtracting means one bit place, exponential constant adding means for adding the bias of the exponent to an output of said exponent shifting means, normalizing means for left-shifting, when a value of the exponent less the bias is odd, a mantissa in said floating-point number input operand one bit place in order to cause the value of the exponent less the bias to be even, table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in an output of said normalizing means as an address, residue holding means for holding a residue when the square root is found by sequentially iterating a fixed number of bits beginning from a high position and descending in a downward order, partial square root value holding means for holding a partial square root value at each iteration, and merged square root value holding means for holding a merged square root value as a combination of the individual partial square root value at each iteration, inverting means for inverting the partial square root value output from said partial square root value holding means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said partial square root value holding means, a residue multiplexer for selecting either a constant O or the residue output from said residue holding means, a multiplicand multiplexer for selecting either the residue output from said residue holding means or an output of said multiplicand generating means, a multiplier multiplexer for selecting either the approximation of square root'"'"'s reciprocal output from said table information storing means or an output of said inverting means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting an output R of said residue multiplexer, an output S of said multiplicand multiplexer, and an output T of said multiplier multiplexer, respectively,operation result shifting means for left-shifting an output of said (R+S×
T+T) operating means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value,a holding data switching multiplexer for selecting either the output of said normalizing means or an output of said operation result shifting means, as an input of said residue holding means, constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said partial square root value holding means, a correcting multiplexer for selecting either the partial square root value output from said partial square root value holding means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correction multiplexer to be merged with the merged square root value output from said merged square root value holding means, and merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means to an output of said digit aligning means in order to output a renewed merged square root value, wherein high-order positions in the output of said (R+S×
T+T) operating means are sequentially held in said partial square root value holding means, as the partial square root value. - View Dependent Claims (20)
-
-
21. A square root operation device to find a square root vector in the order of element on an input operand in the order of element of a vector comprising a floating-point number where a base of an exponent is 2, comprising:
-
a preprocessing unit for performing a preprocess on said input operand, a main unit provided with first through last main circuits the number of which corresponds to that of iterating processes for repeatedly finding a partial square root value until a bit length of a merged square root value as a combination of the individual partial square root values becomes greater than that of a target square root, and a post-processing unit for performing a post-process on an output of said main unit, said preprocessing unit comprising; an input register for holding said input operand, exponential constant subtracting means for removing a bias of the exponent from an exponent part in an output of said input register, exponent holding means for holding an output of said exponential constant subtracting means, normalizing means for left-shifting, when a value of the exponent less the bias is odd, a mantissa part in the output of said input register one bit place in order to cause the value of the exponent less the bias to be even, a normalized operand register for holding an output of said normalizing means, exponent shifting means for right-shifting an output of said exponent holding means one bit place, exponential constant adding means for adding the bias of the exponent to an output of said exponent shifting means, and table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in an output of said normalized operand register as an address, said first main circuit in said main unit comprising; exponent holding means, residue holding means and table output information holding means which are connected to said exponential constant adding means, said normalized operand register and said table information storing means in said preprocessing unit respectively, in order to synchronize pipeline operations, multiplying means for executing a multiplication by inputting an output of said residue holding means as a multiplicand and an output of said table output information holding means as a multiplier so as to output high-order positions in the resulting product as a partial square root value, partial square root value holding means for holding the partial square root value output from said multiplying means, inverting means for inverting the partial square root value output from said partial square root value holding means at each bit, multiplicand generating means for generating a multiplicand from the partial square root value output from said partial square root value holding means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output from said residue holding means, a multiplicand S output from said multiplicand generating means and a multiplier T output from said inverting means, respectively,operation result shifting means for left-shifting an output of said (R+S×
T+T) operating means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value,constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said partial square root value holding means, and a correcting multiplexer for selecting either the partial square root value output from said partial square root value holding means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, said second and subsequent main circuits in said main unit each comprising; exponent holding means, residue holding means, merged square root value holding means and table output information holding means in order to synchronize pipeline operations, multiplying means for executing a multiplication by inputting an output of said residue holding means as a multiplicand and an output of said table output information holding means as a multiplier so as to output high-order positions in the resulting product as the partial square root value, partial square root value holding means for holding the partial square root value output from said multiplying means, inverting means for inverting the partial square root value output from said partial square root value holding means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said partial square root value holding means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output from said residue holding means, a multiplicand S output from said multiplicand generating means and a multiplier T output from said inverting means, respectively,operation result shifting means for left-shifting an output of said (R+S×
T+T) operating means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value,constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said partial square root value holding means, a correcting multiplexer for selecting either the partial square root value output from said partial square root value holding means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with a merged square root value output from said merged square root value holding means, and merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value, wherein; in said second and subsequent main circuits, said exponent holding means is connected to said exponent holding means in the preceding main circuit, said residue holding means is connected to said operation result shifting means in the preceding main circuit, and said table output information holding means is connected to said table output information holding means in the preceding main circuit, in said second main circuit, said merged square root value holding means is connected to said correcting multiplexer in said first main circuit, and in said third and subsequent main circuits, said merged square root value holding means is connected to said merged square root value calculation adding means in the preceding main circuit, said post-processing unit comprising; exponent holding means and merged square root value holding means which are connected to said exponent holding means and said merged square root value holding means in said last main circuit of said main unit respectively in order to synchronize pipeline operations. - View Dependent Claims (22)
-
-
23. A square root operation device to find a square root on an input operand which is normalized in a two bit unit comprising:
-
table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in said input operand as an address, residue holding means for holding a residue when the square root is found by sequentially iterating a fixed number of bits beginning from a high-order position and descending in a downward order, multiplying means for executing a multiplication by inputting the residue output from said residue holding means and the approximation of square root'"'"'s reciprocal output from said table information storing means, as a multiplicand and a multiplier respectively, merged square root value holding means for holding a merged square root value as a combination of individual partial square root values which are high-order positions in the resulting product output from said multiplying means at each iteration, inverting means for inverting the partial square root value output from said multiplying means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said multiplying means, shifting means for left-shifting the residue output from said residue holding means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square too value, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output by said shifting means after shifting, a multiplicand S output from said multiplicand generating means and a multiplier T output from said inverting means, respectively,a holding data switching multiplexer for selecting either said input operand or an output of said (R+S×
T+T) operating means, as an input of said residue holding means,constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said multiplying means, a correcting multiplexer for selecting either the partial square root value output from said multiplying means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with the merged square root value output from said merged square root value holding means, and merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value. - View Dependent Claims (24)
-
-
25. A square root operation device to find a square root on an input operand which is normalized in a two bit unit, comprising:
-
table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in said input operand as an address, residue holding means for holding a residue when the square root is found by sequentially iterating a fixed number of bits beginning from a high-order position and descending in a downward order, partial square root value holding means for holding a partial square root value at each iteration, and merged square root value holding means for holding a merged square root value as a combination of the individual partial square root values at each iteration, shifting means for left-shifting the residue output from said residue holding means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value, inverting means for inverting the partial square root value output from said partial square root value holding means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said partial square root value holding means, a residue multiplexer for selecting either a constant 0 or a residue output by said shifting means after shifting, a multiplicand multiplexer for selecting either the residue output from said residue holding means or an output of said multiplicand generating means, a multiplier multiplexer for selecting either the approximation of square root'"'"'s reciprocal output from said table information storing means or an output of said inverting means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting an output R of said residue multiplexer, an output S of said multiplicand multiplexer, and an output T of said multiplier multiplexer, respectively,a holding data switching multiplexer for selecting either said input operand or an output of said (R+S×
T+T) operating means, as an input of said residue holding means,constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said partial square root value holding means, a correcting multiplexer for selecting either the partial square root value output from said partial square root value holding means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with the merged square root value output from said merged square root value holding means, and merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value, wherein high-order positions in the output of said (R+S×
T+T) operating means are sequentially held in said partial square root value holding means, as the partial square root value. - View Dependent Claims (26)
-
-
27. A square root operation device to find a square root on an input operand which is normalized in a two bit unit, comprising:
-
table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in said input operand as an address, residue holding means for holding a residue when the square root is found by sequentially iterating a fixed number of bits beginning from a high-order position and descending in a downward order, multiplying means for executing a multiplication by inputting the residue output from said residue holding means and the approximation of square root'"'"'s reciprocal output from said table information storing means, as a multiplicand and a multiplier respectively, merged square root value holding means for holding a merged square root value as a combination of individual partial square root values which are high-order positions in the resulting product output from said multiplying means at each iteration, inverting means for inverting the partial square root value output from said multiplying means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output from said multiplying means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting a residue R output from said residue holding means, a multiplicand S output from said multiplicand generating means, and a multiplier T output from said inverting means, respectively,shifting means for left-shifting an output of said (R+S×
T+T) operating means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value,a holding data switching multiplexer for selecting either said input operand or an output of said shifting means, as an input of said residue holding means, constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said multiplying means, a correcting multiplexer for selecting either the partial square root value output from said multiplying means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with the merged square root value output from said merged square root value holding means, and merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value. - View Dependent Claims (28)
-
-
29. A square root operation device to find a square root on an input operand which is normalized in a two bit unit, comprising:
-
table information storing means for indexing an approximation of square root'"'"'s reciprocal by designating high-order bits in said input operand as an address, residue holding means for holding a residue when the square root is found by sequentially iterating a fixed number of bits beginning from a high-order position and descending in a downward order, partial square root value holding means for holding a partial square root value at each iteration, and merged square root value holding means for holding a merged square root value as a combination of the individual partial square root values at each iteration, inverting means for inverting the partial square root value output from said partial square root value holding means at every bit, multiplicand generating means for generating a multiplicand by left-shifting an output of said merged square root value holding means one bit place, with the partial square root value output form said partial square root value holding means, a residue multiplexer for selecting either a constant 0 or the residue output from said residue holding means, a multiplicand multiplexer for selecting either the residue output from said residue holding means or an output of said multiplicand generating means, a multiplier multiplexer for selecting either the approximation of square root'"'"'s reciprocal output from said table information storing means or an output of said inverting means, (R+S×
T+T) operating means for executing the operation (R+S×
T) or the operation (R+S×
T+T) by inputting an output R of said residue multiplexer, an output S of said multiplicand multiplexer, and an output T of said multiplier multiplexer, respectively,shifting means for left-shifting an output of said (R+S×
T+T) operating means by a difference obtained by subtracting a bit length overlapping between the adjacent partial square root values from a bit length of the partial square root value,a holding data switching multiplexer for selecting either said input operand or an output of said shifting means, as an input of said residue holding means, constant subtracting means for subtracting 1 from a least significant bit in the partial square root value output from said partial square root value holding means, a correcting multiplexer for selecting either the partial square root value output from said partial square root value holding means or an output of said constant subtracting means so as to output the one thus selected as a corrected partial square root value, digit aligning means for carrying out a digit adjustment to enable the corrected partial square root value output from said correcting multiplexer to be merged with the merged square root value output from said merged square root value holding means, and merged square root value calculation adding means for adding the merged square root value output from said merged square root value holding means and an output of said digit aligning means in order to output a renewed merged square root value, wherein high-order positions in the output of said (R+S×
T+T) operating means are sequentially held in said partial square root value holding means, as the partial square root value. - View Dependent Claims (30)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
-
Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
-
InventorsNakano, Hiraku
-
Primary Examiner(s)Nguyen, Long T.
-
Assistant Examiner(s)Ngo, Chuong D.
-
Application NumberUS07/893,089Time in Patent Office587 DaysField of Search364/748, 364/751, 364/752US Class Current708/605CPC Class CodesG06F 7/5525 Roots or inverse roots of s...
