Memory device comprising thin film memory transistors

• US 5,278,790 A
• Filed: 06/04/1991
• Issued: 01/11/1994
• Est. Priority Date: 05/15/1989
• Status: Expired due to Term

• Current Assignee: Casio Computer Company Limited
• Original Assignee: Casio Computer Company Limited
• Inventors: Kanabara, Minoru
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): Cunningham, Terry D.
• Application Number:
  US07/710,057
• Time in Patent Office: 952 Days
• Field of Search: 365/189.05, 365/230.06, 365/235, 365/239, 365/168, 257/66
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches

Abstract

A latch circuit is provided between a column switch connected to the input/output sides for selecting data lines and a tristate buffer connected to the write side of a memory array, or between the column switch and a sense amplifier connected to the readout side of the memory array. The latch circuit has a capacity corresponding to a plurality of data contents in the tristate buffer or the sense amplifier. While data set in a portion of the latch circuit is being output, the next data can be set in another portion of the latch circuit.

Claims

1. A memory system comprising:

a memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory elements, each of said memory elements being connected to one of said word lines and one of said data lines;

word line designating means for designating one of said word lines of said memory array, for effecting data readout from said memory array and wiring of data into said memory array;

sense amplifier means for discriminating data read out from said memory array;

latch means for latching data to be written into and read out from said memory array, said latch means having a plurality of latch elements, the number of said latch elements corresponding to the number of memory elements connected to a plurality of word lines of said memory array;

data supply means for supplying the data to said latch means;

respective data for connecting said data lines of said memory array to said sense amplifier means, for connecting said sense amplifier means to said latch means, for connecting said latch means to said data line of said memory array, and for connecting said data supply means to said latch means; and

read/write means including;

write means for writing the data latched in said latch means into said memory array as a batch, wherein the number of data written into said memory elements at one time corresponds to the number of memory elements connected to one word line; and

readout means for reading out the data from said memory array to said sense amplifier means and for transferring said data from said sense amplifier means to said latch means as a batch, wherein the number of data transferred to said latch means at one time corresponds to the number of memory elements connected to one word line.

2. The memory system according to claim 1, wherein said sense amplifier means includes:

a flip-flop circuit having a positive feedback circuit;

control voltage supplying means for supplying an operation voltage to said flip-flop circuit to set a high-level voltage and a low-level voltage; and

switching means for outputting said high-level and low-level voltages to the outside of said sense amplifier means.

3. The memory system according to claim 1, wherein each of said memory elements is formed by a thin-film transistor.

4. The memory system according to claim 1, wherein said latch means comprises thin-film transistors.

5. The memory system according to claim 1, wherein said sense amplifier means comprises thin-film transistors.

6. The memory system according to claim 1, wherein the read/write means includes a thin-film transistor.

7. The memory system according to claim 1, wherein said word line designating means includes a thin-film transistor.

8. The memory system according to claim 1, wherein said word line designating means includes a buffer circuit including a booster circuit provided between a final output stage and a preceding-stage circuit, and wherein an output signal from the preceding-stage circuit is boosted and is input to a gate electrode of a transistor in the final output stage.

9. The memory system according to claim 1, wherein said write means includes:

a NOR circuit to which an enable signal is input; and

a boostrap circuit having a booster circuit, an input signal to said boostrap circuit being controlled by the NOR circuit to enhance a driving performance relating to a load.