Flexible addressing for drams

• US 5,278,801 A
• Filed: 08/31/1992
• Issued: 01/11/1994
• Est. Priority Date: 08/31/1992
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Ward, Raymond A., Dresser, Scott A.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/938,113
• Time in Patent Office: 498 Days
• Field of Search: 365/189.02, 365/230.02, 365/189.01, 365/230.01, 365/233, 365/230.05
• US Class Current: 365/230.02
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory controller for controlling access to a memory includes a mapper for mapping a physical address to a row address and a column address that are suitable for addressing first and second memory devices having the same memory capacity but different addressing formats, a multiplexer for multiplexing the row address and the column address onto a set of address lines for addressing the memory and a circuit for generating control signals for controlling access to the memory. In a preferred embodiment, the first memory devices are 16 Mb DRAMs which require asymmetric addressing, and the second memory devices are 16 Mb DRAMs which require symmetric addressing. The memory controller of the invention generates a row address and a column address for addressing both types of memory devices without having knowledge of the types of memory devices that are present in the memory.

Claims

1. A memory controller for controlling access to a memory, comprising:

a means for mapping a physical address to a row address and a column address, that are suitable for addressing first memory devices having a first address format and second memory devices having a second address format, said first and second memory devices having the same memory capacity;

means for multiplexing said row address and said column address onto a set of address lines for addressing the memory; and

means for generating control signals for controlling access to the memory by said row address and said column address.

2. A memory controller as defined in claim 1 wherein the first memory devices and the second memory devices require different numbers of column address bits and different numbers of row address bits.

3. A memory controller as defined in claim 1 wherein said means for mapping generates a row address and a column address that is suitable for addressing first memory devices comprising 16 Mb DRAMs which require a 12 bit row address and a 10 bit column address, and second memory devices comprising 16 Mb DRAMs which require an 11 bit row address and an 11 bit column address.

4. A memory controller as defined in claim 3, wherein said means for mapping generates a 12 bit row address and a 11 bit column address.

5. A memory controller as defined in claim 1 wherein said means for mapping includes means for mapping at least one bit of the physical address into both the row address and the column address.

6. A memory controller as defined in claim 2 wherein said means for mapping generates a row address and a column address having equal numbers of bits.

7. In a data processing system having a microprocessor that generates memory access requests which includes address bits of a memory block, a memory controller for responding to the memory access requests, and a memory, said memory comprising multiple memory chips of the same memory capacity, wherein at least one of said memory chips requires a symmetric addressing format and at least one of said chips requires an asymmetric addressing format, said memory controller comprising:

a) an address mapper for mapping the address bits of each memory access request into a row address and a column address, wherein at least one of the address bits is mapped to both the row address and the column address; and

b) means for forwarding the row address and the column address to the memory.

8. In a data processing system having a microprocessor that generates memory access requests which include address bits of a block of memory, a memory subsystem, comprising:

a) a memory comprising memory chips of the same memory capacity, wherein at least one of said memory chips requires a symmetric address and at least one of said memory chips requires an asymmetric address; and

b) a memory controller for responding to the memory access requests, comprising;

i) an address mapper for mapping the address bits of each memory access request into a row address and a column address wherein at least one of the address bits is mapped to both the row address and the column address; and

ii) means for forwarding the row address and the column address to the memory such that any extra bits in the column address or the row address are ignored by the memory.

9. A memory subsystem as recited in claim 8 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

10. Memory subsystem as recited in claim 9 wherein the memory chips comprise 16 megabit DRAM chips.

11. A memory subsystem as recited in claim 8 wherein the memory chips are organized into single in line memory modules (SIMMs).

12. A memory subsystem as recited in claim 11 wherein the memory chips comprise 16 megabit DRAM chips.

13. A memory subsystem as recited in claim 8 further comprising at least one additional memory chip of a memory capacity that differs from the memory capacity of other of the memory chips.

14. In a data processing system having a microprocessor, memory having at least one memory chip that employs symmetric addressing and at least one memory chip that employs asymmetric addressing, a memory controller and a microprocessor, a method comprising the steps of:

a) receiving at the memory controller a memory block address from the microprocessor of a memory location to be accessed;

b) mapping the memory block address from the microprocessor into a row address and a column address such that at least one bit in the memory block address is mapped to both the row address and the column address;

c) forwarding said row address and said column address to the memory chips of the memory regardless of whether said memory chips employ symmetric addressing or asymmetric addressing; and

d) ignoring at the memory chips, extra bits provided in the row address or the column address so that the memory block is accessed.