Method and apparatus for transition direction coding

• US 5,278,902 A
• Filed: 12/30/1992
• Issued: 01/11/1994
• Est. Priority Date: 12/30/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nugent, Steven F.
• Primary Examiner(s): Buczinski, Stephen C.
• Application Number:
  US07/998,527
• Time in Patent Office: 377 Days
• Field of Search: 395/550, 371/1, 375/118, 380/42
• US Class Current: 380/42
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof
• CPC Class Codes: H04L 25/4908 using mBnB codes

Abstract

The present invention provides a method and apparatus for encoding data in the context of a digital system for communicating binary information, including code words, over a communications channel. The information communicated over the channel is synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, where a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction. The present invention encodes data words of n-bits each into a plurality of code words of m-bits each by selecting from the set of m-bit binary numbers those binary numbers in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit to that bit. Each of the selected binary numbers is a code word. Each data word is preferably associated with a code word. Data words are preferably formed into a message, and each code word associated with each data word of the message is longitudinally serialized so that each code word is represented by a serial bit pattern. The associated code words of the message are then transmitted in parallel with each other in a plurality of groups or "stacks".

Claims

1. In a digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, said binary information including a plurality of code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, an encryption device comprising:

an encoder means for providing a plurality of code words in response to a plurality of data words associated with said code words; and

a parallel to serial converter means for providing a plurality of stacks over said channel, each said stack comprising a plurality of code words, each code word being transmitted in serial form at the same time as each other code word in the stack,

each said code word comprising an m-bit binary number in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit.

2. The encryption device of claim 1,

said encoder means comprising:

a first encoder look-up table means for providing an odd code word in response to an n-bit data word received during one of a plurality of input clock edges during one of a plurality of first states, and

a second encoder look-up table means for providing an even code word in response to an n-bit data word received during one of said input clock edges during one of a plurality of second states, said first and second states alternating in time,

each said odd code word comprising a code word in which the first of said system clock edges associated with said code word is in a first direction,

each said even code word comprising a code word in which the first of said system clock edges associated with said code word is in a second direction; and

said parallel to serial converter means comprising;

a plurality of first shift register means for receiving a plurality of said odd code words in parallel form from said first encoder look-up table means during the first state and unloading said odd code words in serial form to produce one of a plurality of odd stacks; and

a plurality of second shift register means for receiving a plurality of said even code words in parallel form from said second encoder look-up table means during the second state and unloading said even code words in serial form to produce one of a plurality of even stacks; and

said encryption device further comprising;

encoder state control means, coupled to said first and second encoder look-up table means and said pluralities of first and second shift register means, for controlling said first and second encoder look-up table means and said pluralities of first and second shift register means in said first and second states.

3. The encryption device of claim 2, wherein each said first shift register means successively broadside loads an odd code word during successive input clock edges in the first state and, after each said first shift register means has been loaded, said plurality of first shift register means serially unloads said odd code words to provide said odd stack during the subsequent second state;

and

each said second shift register means successively broadside loads an even code word during successive input clock edges in the second state and, after each said second shift register means has been loaded, said plurality of second shift register means serially unloads said even code words to provide said even stack during the subsequent first state.

4. The encryption device of claim 3, wherein

for m even, said first shift register means includes a first delimiter register means for storing a "1" bit after each said odd code word, and said second shift register means includes a second delimiter register means for storing a "0" bit after each said even code word.

5. The encryption device of claim 3, further comprising a system clock shift register means for, during the second state, providing an m-bit word of alternating ones and zeros beginning with a one bit, and, during the first state, providing an m-bit word of alternating ones and zeros beginning with a zero bit.

6. The encryption device of claim 2,

said first encoder look up table means further comprising means for providing an odd code word from either a first or a second odd table in response to a first or a second odd selection signal, respectively, said odd code word associated with corresponding positions in the odd and even stacks;

said first odd table being comprised of odd code words in which the first bit is a one,

said second odd table being comprised of odd code words in which the first bit either is a one or a zero;

said second encoder look up table means further comprising means for providing an even code word from either a first or a second even table in response to a first or a second even selection signal, respectively, said even code word associated with corresponding positions in the odd and even stacks;

said first even table being comprised of even code words in which the first bit either is a one or a zero,

said second even table being comprised of even code words in which the first bit is a zero;

said encryption device further comprising selection logic means for;

testing the last bit of a previous even code word stored in each said second shift register means, and providing said first odd selection signal if the last bit of the previous even code word occupying the corresponding position in the stack as the odd code word is a one, and providing said second odd selection signal if the last bit of the previous even code word occupying the corresponding position in the stack as the odd code word is a zero,

testing the last bit of a previous odd code word stored in each said first shift register means, and providing said first even selection signal if the last bit of the previous odd code word occupying the corresponding position in the stack as the even code word is a one, and providing said second even selection signal if the last bit of the previous odd code word occupying the corresponding position in the stack as the even code word is a zero.

7. In a digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, said binary information including a plurality of code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, a decryption device comprising:

serial to parallel converter means for receiving a plurality of stacks of code words over said channel and providing said code words in parallel form; and

decoder means, coupled to said serial to parallel converter means, for receiving said code words in parallel form and for providing a plurality of corresponding data words in response to said code words,

each code word comprising an m-bit binary number in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit,

each stack comprising a plurality of code words communicated as a serial bit pattern over said channel at the same time as each other code word in the stack.

8. The decryption device of claim 7, wherein said stacks comprise a plurality of odd and even stacks alternating in time,

each said odd stack comprising a plurality of odd code words, each said odd code word being communicated as a serial bit pattern over said channel at the same time as each other odd code word within said odd stack,

each said odd code word comprising a code word in which the first of said system clock edges associated with said code word is in a first direction,

each said even stack comprising a plurality of even code words, each said even code word being communicated as a serial bit pattern over said channel at the same time as each other even code word within said even stack,

each said even code word comprising a code word in which the first of said system clock edges associated with said code word is in a second direction;

and

said decryption device further comprising;

decoder state control means, coupled to said serial to parallel converter means and said decoder means, for controlling said serial to parallel converter means and said decoder means.

9. The decryption device of claim 8, said serial to parallel converter means comprising:

a plurality of first odd shift register means, each first odd shift register means for serially loading a plurality of first alternating bits of an odd stack code word during a plurality of rising system clock pulse edges in a first decoder state, and for broadside unloading said first alternating bits of said odd stack code word in response to an odd full signal in a second decoder state, said first and second decoder states alternating in time;

a plurality of second odd shift register means, each second odd shift register means for serially loading a plurality of second alternating bits of an odd stack code word during a plurality of falling system clock pulse edges in the first decoder state, and for broadside unloading said second alternating bits of said odd stack code word in response to said odd full signal in the second decoder state,

a plurality of first even shift register means, each first even shift register means for serially loading a plurality of first alternating bits of an even stack code word during a plurality of rising system clock pulse edges in the second decoder state, and for broadside unloading said first alternating bits of said even stack code word in response to an even full signal in the first decoder state;

a plurality of second even shift register means, each second even shift register means for serially loading a plurality of second alternating bits of an even stack code word during a plurality of falling system clock pulse edges in the second decoder state, and for broadside unloading said second alternating bits in response to said even full signal in the first decoder state,

routing means for interleaving said first and second alternating bits of each odd stack code word to provide each odd stack code word in parallel form to said decoder means, and for interleaving said first and second alternating bits of each even stack code word to provide each even stack code word in parallel form to said decoder means;

said decoder state control means providing said odd full signal when said first and second odd shift registers are fully loaded, and providing said even full signal when said first and second even shift registers are fully loaded; and

said decoder means comprising a plurality of decoder look up table means, each decoder look up table means for receiving a code word and providing a corresponding data word.

10. The decryption device of claim 9,

each decoder look up table means further comprising means for using either a first or a second decoding table for decoding each code word into either a first or a second data word associated with said code word, in response to a first or a second decoder selection signal, respectively;

said first decoding table being comprised of data words in which the code words associated with said data words are those odd code words in which the first bit is a one, and those even code words in which the first bit is a one or a zero,

said second decoding table being comprised of data words in which the code words associated with said data words are those odd code words in which the first bit is a one or a zero, and those even code words in which the first bit is a zero,

said decryption device further comprising decoder selection logic means for;

testing the last bit of a previous code word received by each decoder look up table means, and providing said first decoder selection signal if the last bit of the previous code word is a one, and providing said second decoder selection signal if the last bit of the previous code word is a zero.

11. In a digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, said binary information including a plurality of code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, an encryption device comprising:

an encoder for providing a plurality of code words in response to a plurality of data words associated with said code words; and

a parallel to serial converter responsive to said code words for providing a plurality of stacks over said channel, each said stack comprising a plurality of code words, each code word being transmitted in serial form at the same time as each other code word in the stack,

each said code word comprising an m-bit binary number in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit.

12. The encryption device of claim 11,

said encoder comprising:

a first encoder look-up table for providing an odd code word in response to an n-bit data word received during one of a plurality of input clock edges during one of a plurality of first states, and

a second encoder look-up table for providing an even code word in response to an n-bit data word received during one of said input clock edges during one of a plurality of second states, said first and second states alternating in time,

each said odd code word comprising a code word in which the first of said system clock edges associated with said code word is in a first direction,

each said even code word comprising a code word in which the first of said system clock edges associated with said code word is in a second direction; and

said parallel to serial converter comprising;

a plurality of first shift registers for receiving a plurality of said odd code words in parallel form from said first encoder look-up table during the first state and unloading said odd code words in serial form to produce one of a plurality of odd stacks; and

a plurality of second shift registers for receiving a plurality of said even code words in parallel form from said second encoder look-up table during the second state and unloading said even code words in serial form to produce one of a plurality of even stacks; and

said encryption device further comprising;

an encoder state machine, coupled to said first and second encoder look-up tables and said pluralities of first and second shift registers, for controlling said first and second encoder look-up tables and said pluralities of first and second shift registers in said first and second states.

13. The encryption device of claim 12, wherein each said first shift register successively broadside loads an odd code word during successive input clock edges in the first state and, after each said first shift register has been loaded, said plurality of first shift registers serially unloads said odd code words to provide said odd stack during the subsequent second state;

and

each second shift register successively broadside loads an even code word during successive input clock edges in the second state and, after each said second shift register has been loaded, said plurality of second shift registers serially unloads said even code words to provide said even stack during the subsequent first state.

14. The encryption device of claim 13, wherein

for m even, each first shift register includes a first delimiter register for storing a "1" bit after each odd code word, and each second shift register includes a second delimiter register for storing a "0" bit after each even code word.

15. The encryption device of claim 13, further comprising a system clock shift register for, during the second state, providing an m-bit word of alternating ones and zeros beginning with a one bit, and, during the first state, providing an m-bit word of alternating ones and zeros beginning with a zero bit.

16. The encryption device of claim 12,

said first encoder look up table further comprising a first and a second odd table of odd code words responsive to a first and a second odd selection signal;

said first odd table being comprised of odd code words in which the first bit is a one,

said second odd table being comprised of odd code words in which the first bit either is a one or a zero;

said second encoder look up table further comprising a first and a second even table responsive to a first and a second even selection signal;

said first even table being comprised of even code words in which the first bit either is a one or a zero,

said second even table being comprised of even code words in which the first bit is a zero;

said encryption device further comprising a selection logic circuit for;

testing the last bit of a previous even code word stored in each said second shift register, and providing said first odd selection signal if the last bit of the previous even code word occupying the corresponding position in the stack as the odd code word is a one, and providing said second odd selection signal if the last bit of the previous even code word occupying the corresponding position in the stack as the odd code word is a zero,

testing the last bit of a previous odd code word stored in each said first shift register, and providing said first even selection signal if the last bit of the previous odd code word occupying the corresponding position in the stack as the even code word is a one, and providing said second even selection signal if the last bit of the previous odd code word occupying the corresponding position in the stack as the even code word is a zero.

17. In a digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, said binary information including a plurality of code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, a decryption device comprising:

a serial to parallel converter for receiving a plurality of stacks of code words over said channel and providing said code words in parallel form; and

a decoder, coupled to said serial to parallel converter, for receiving said code words in parallel form and for providing a plurality of corresponding data words in response to said code words,

each code word comprising an m-bit binary number in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit,

each stack comprising a plurality of code words communicated as a serial bit pattern over said channel at the same time as each other code word in the stack.

18. The decryption device of claim 17, wherein said stacks comprise a plurality of odd and even stacks alternating in time,

each said odd stack comprising a plurality of odd code words, each said odd code word being communicated as a serial bit pattern over said channel at the same time as each other odd code word within said odd stack,

each said odd code word comprising a code word in which the first of said system clock edges associated with said code word is in a first direction,

each said even stack comprising a plurality of even code words, each said even code word being communicated as a serial bit pattern over said channel at the same time as each other even code word within said even stack,

each said even code word comprising a code word in which the first of said system clock edges associated with said code word is in a second direction;

and said decryption device further comprising;

a decoder state machine, coupled to said serial to parallel converter and said decoder, for controlling said serial to parallel converter and said decoder.

19. The decryption device of claim 18, said serial to parallel converter comprising:

a plurality of first odd shift registers, each first odd shift register adapted to serially load a plurality of first alternating bits of an odd stack code word during a plurality of rising system clock pulse edges in a first decoder state, and to broadside unload said first alternating bits of said odd stack code word in response to an odd full signal in a second decoder state, said first and second decoder states alternating in time;

a plurality of second odd shift registers, each second odd shift register adapted to serially load a plurality of second alternating bits of an odd stack code word during a plurality of falling system clock pulse edges in the first decoder state, and to broadside unload said second alternating bits of said odd stack code word in response to said odd full signal in the second decoder state,

a plurality of first even shift registers, each first even shift register means adapted to serially load a plurality of first alternating bits of an even stack code word during a plurality of rising system clock pulse edges in the second decoder state, and to broadside unload said first alternating bits of said even stack code word in response to an even full signal in the first decoder state;

a plurality of second even shift registers, each second even shift register adapted to serially load a plurality of second alternating bits of an even stack code word during a plurality of falling system clock pulse edges in the second decoder state, and to broadside unload said second alternating bits in response to said even full signal in the first decoder state,

a routing circuit for interleaving said first and second alternating bits of each odd stack code word to provide each odd stack code word in parallel form to said decoder, and for interleaving said first and second alternating bits of each even stack code word to provide each even stack code word in parallel form to said decoder;

said decoder state machine providing said odd full signal when said first and second odd shift registers are fully loaded, and providing said even full signal when said first and second even shift registers are fully loaded; and

said decoder comprising a plurality of decoder look up tables, each decoder look up table adapted to receive a code word and provide a corresponding data word.

20. The decryption device of claim 19,

each decoder look up table further comprising a first and a second decoding table for decoding each code word into either a first or a second data word associated with said code word, in response to a first or a second decoder selection signal, respectively;

said first decoding table being comprised of data words in which the code words associated with said data words are those odd code words in which the first bit is a one, and those even code words in which the first bit is a one or a zero,

said second decoding table being comprised of data words in which the code words associated with said data words are those odd code words in which the first bit is a one or a zero, and those even code words in which the first bit is a zero,

said decryption device further comprising a decoder selection logic circuit for;

testing the last bit of a previous code word received by each decoder look up table, and providing said first decoder selection signal if the last bit of the previous code word is a one, and providing said second decoder selection signal if the last bit of the previous code word is a zero.

21. In a digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of clock pulses having edges associated with the binary information, said binary information including code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, an apparatus for encoding data words of n bits each into a plurality of code words of m bits each, the apparatus comprising:

selection means for selecting from a plurality of m-bit binary numbers those binary numbers in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit; and

assignment means for associating each data word with one of said selected binary numbers.

22. In a digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, said binary information including a plurality of code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, a method of encoding data words of n bits each into a plurality of code words of m bits each, comprising the step of:

selecting from a plurality of m-bit binary numbers those binary numbers in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit, wherein each of said selected binary numbers is a code word.

23. The method of claim 22, further comprising the step of:

associating each data word with one of said code words.

24. In a digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, said binary information including a plurality of code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, a method of communicating a plurality of code words, comprising the steps of:

forming a message comprising a plurality of data words, each data word associated with at least one code word, wherein

each code word is an m-bit binary number in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit;

longitudinally serializing each code word associated with each data word of the message, so that each code word is represented by a serial bit pattern; and

transmitting the associated serialized code words of the message in parallel with each other in a plurality of stacks.

25. The method of claim 24, wherein at least one of said stacks is an odd stack of code words comprising those code words selected from a set of odd code words wherein the first of said system clock edges associated with each of said odd code words is in a first direction.

26. The method of claim 25, wherein at least one of said stacks is an even stack of code words comprising those code words selected from a set of even code words wherein the first of said system clock edges associated with each of said even code words is in a second direction.

27. The method of claim 26, wherein the code words in a first stack are selected from the set of odd code words and the code words in the next consecutive stack are selected from the set of even code words, the code words in subsequent stacks being selected in the same alternating manner.

28. The method of claim 27, wherein each pair of consecutive stacks is separated by at least one clock pulse, said method further comprising the step of transmitting a delimiter word between each pair of code words in consecutive stacks, wherein the bits of each said delimiter word do not experience a transition in a direction opposite to that of the associated system clock edges occurring between the transmission of the stacks.

29. The method of claim 27, further comprising the steps of, for m odd:

in each odd stack, transmitting odd code words in which the first bit of an odd code word is a one if the last bit of a previous even code word occupying the corresponding position in the stack as the odd code word is a one, and transmitting odd code words in which the first bit of an odd code word is a one or a zero if the last bit of a previous even code word occupying the corresponding position in the stack as the odd code word is a zero; and

in each even stack, transmitting even code words in which the first bit of an even code word is a one or a zero if the last bit of a previous odd code word occupying the corresponding position in the stack as the even code word is a one, and transmitting even code words in which the first bit of an even code word is a zero if the last bit of a previous odd code word occupying the corresponding position in the stack as the even code word is a zero.

30. The method of claim 24, wherein a plurality of code words are not associated with any of said data words, and at least one of said code words not associated with any of said data words is associated with a pad word, said method further comprising the step of transmitting at least one pad word in one of said stacks of said message.

31. The method of claim 24, wherein a plurality of code words are not associated with any of said data words, and one of said code words not associated with any of said data words is associated with an end of message word, said method further comprising the step of transmitting said end of message word as the last word in the last stack of said message.

32. The method of claim 24, further comprising the step of selecting only those code words that have either an odd or an even number of binary ones, wherein said code words also serve as longitudinal parity check codes.

33. The method of claim 24, wherein the number of bits per code word m is determined according to the equation:

space="preserve" listing-type="equation">m=the smallest integer greater than [(1.5×

n)-0.5].

34. The method of claim 24, further comprising the steps of:

receiving the plurality of stacks of associated code words of the message;

converting each serialized code word to parallel form;

addressing a look up table with each converted code word to recover the data word associated with each code word, wherein each data word is stored in said look up table at an address designated by the code word associated with each said data word.

35. In a digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, said binary information including code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, said code comprising:

a plurality of code words of m bits each representing a plurality of data words of n bits each, each said code word comprising an m-bit binary number in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit.

36. A digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, said binary information including a plurality of code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, the system comprising:

processing means for processing information;

memory means for storing information;

said communications channel comprising a bus means for communicating information;

said processor means and said memory means each having an interface means for coupling said processor means and said memory means to said bus means,

at least one of said interface means having an encryption device comprising;

encoder means for providing a plurality of code words in response to a plurality of data words associated with said code words; and

parallel to serial converter means for providing a plurality of stacks over said channel, each said stack comprising a plurality of code words, each code word being transmitted in serial form at the same time as each other code word in the stack,

each said code word comprising an m-bit binary number in which each bit either experiences a transition in the same direction as one of said system clock edges associated with that bit or experiences no transition from a prior adjacent bit; and

at least one of said interface means having a decryption device comprising;

serial to parallel converter means for receiving said stacks of code words over said channel and providing said code words in parallel form; and

decoder means, coupled to said serial to parallel converter means, for receiving said code words in parallel form and for providing a plurality of associated data words in response to said code words.

37. A digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, said binary information including a plurality of code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, the system comprising:

a plurality of processor means for processing information;

a plurality of message routing means coupled to each other for routing binary information over said channel;

a plurality of interface means for interfacing each said processor means to a message routing means,

at least one of said interface means having an encryption device comprising;

encoder means for providing a plurality of code words in response to a plurality of data words associated with said code words; and

parallel to serial converter means for providing a plurality of stacks over said channel, each said stack comprising a plurality of code words, each code word being transmitted in serial form at the same time as each other code word in the stack,

each said code word comprising an m-bit binary number in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit; and

at least one of said interface means having a decryption device comprising;

serial to parallel converter means for receiving said stacks of code words over said channel and providing said code words in parallel form; and

decoder means, coupled to said serial to parallel converter means, for receiving said code words in parallel form and for providing a plurality of associated data words in response to said code words.

38. A digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, said binary information including a plurality of code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, the system comprising:

a processor for processing information;

a memory for storing information;

said communications channel comprising a bus for communicating information;

said processor and said memory each having an interface for coupling said processor and said memory to said bus,

at least one of said interfaces having an encryption device comprising;

an encoder for providing a plurality of code words in response to a plurality of data words associated with said code words; and

a parallel to serial converter for providing a plurality of stacks over said channel, each said stack comprising a plurality of code words, each code word being transmitted in serial form at the same time as each other code word in the stack,

each said code word comprising an m-bit binary number in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit; and

at least one of said interfaces having a decryption device comprising;

a serial to parallel converter for receiving said stacks of code words over said channel and providing said code words in parallel form; and

a decoder, coupled to said serial to parallel converter, for receiving said code words in parallel form and for providing a plurality of associated data words in response to said code words.

39. A digital system for communicating binary information over a communications channel synchronized by a system clock producing a plurality of system clock pulses having edges associated with the binary information, said binary information including a plurality of code words, wherein a change in the bit pattern between a bit and a prior adjacent bit represents a transition having a direction, the system comprising:

a plurality of processors for processing information;

a plurality of message routers coupled to each other for routing binary information over said channel;

a plurality of interfaces for interfacing each said processor to a message router,

at least one of said interfaces having an encryption device comprising;

an encoder for providing a plurality of code words in response to a plurality of data words associated with said code words; and

a parallel to serial converter for providing a plurality of stacks over said channel, each said stack comprising a plurality of code words, each code word being transmitted in serial form at the same time as each other code word in the stack,

each said code word comprising an m-bit binary number in which each bit either experiences a transition in the same direction as the system clock edge associated with that bit or experiences no transition from a prior adjacent bit; and

at least one of said interfaces having a decryption device comprising;

a serial to parallel converter for receiving said stacks of code words over said channel and providing said code words in parallel form; and

a decoder, coupled to said serial to parallel converter, for receiving said code words in parallel form and for providing a plurality of associated data words in response to said code words.