Method of testing individual dies on semiconductor wafers prior to singulation

• US 5,279,975 A
• Filed: 02/07/1992
• Issued: 01/18/1994
• Est. Priority Date: 02/07/1992
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Higgins, Brian, Devereaux, Kevin M., Bunn, Mark
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US07/832,785
• Time in Patent Office: 711 Days
• Field of Search: 437/226, 437/227, 437/8, 148/DIG. 28, 371/21.4, 371/21.6
• US Class Current: 438/18
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method of processing and testing a semiconductor wafer containing an array of integrated circuit dies comprises: a) providing die test cycling circuitry on the wafer b) etching contact openings through a passivation layer atop the wafer to Vcc and Vss pads associated with individual dies; c) patterning a layer of conductive material atop the water to provide a Vcc bus and a Vss bus which interconnect with the Vcc and Vss pads respectively, the Vcc bus electrically connecting with the test cycling circuitry; d) burn-in testing the wafer with selected voltages being applied to the Vss and Vcc buses e) etching the Vcc bus and Vss bus from the wafer; f) etching contact openings through the passivation layer to conductive pads on individual dies; g) testing the individual dies for operability by engaging the conductive pads with testing equipment; h) identifying operable dies; i) singulating the dies; and j) collecting the operable dies.

Claims

1. A method of processing and of testing a semiconductor wafer containing an array of integrated circuit dies, the wafer including areas of individual die circuitry and areas of distinct scribe line area which are separate from the individual die circuitry areas, the method comprising the following steps:

providing die test cycling circuitry on the wafer for test cycling individual dies;

providing a passivation layer atop the wafer;

etching contact openings through the passivation layer to Vcc and Vss pads associated with individual dies;

providing a layer of conductive material atop the wafer;

patterning the layer of conductive material to provide a Vcc bus and a Vss bus atop the dies which interconnect with the Vcc and Vss pads respectively, the Vcc and Vss busses each including respective straight-line bus portions extending fully between individual die circuitry areas, each straight-line portion overlying a plurality of the individual die circuitry areas, the Vcc bus electrically connecting with the test cycling circuitry;

burn-in testing the wafer with voltages being applied to the Vss and Vcc buses to cycle the individual dies during burn-in testing;

etching the Vcc bus and Vss bus from the wafer;

etching contact openings through the passivation layer to conductive pads on individual dies;

testing the individual dies on the wafer for operability by engaging the conductive pads with testing equipment;

identifying operable and inoperable dies;

severing through the wafer to singulate the dies; and

collecting the operable dies.

2. The method of processing and of testing a semiconductor wafer of claim 1 wherein the array includes scribe line area between and separating individual dies, and further comprising providing the test cycling circuitry in the scribe line area.

3. The method of processing and of testing a semiconductor wafer of claim 1 wherein the step of providing die test cycling circuitry comprises providing individual test cycling circuitry associated with individual dies.

4. The method of processing and of testing a semiconductor wafer of claim 3 further comprising providing the individual test cycling circuitry on the individual dies.

5. The method of processing and of testing a semiconductor wafer of claim 3 wherein the array includes scribe line area between and separating individual dies, and further comprising providing the individual test cycling circuitry in the scribe line area.

6. The method of processing and of testing a semiconductor wafer of claim 1 further comprising utilizing the test cycling circuitry to:

write data to the dies and read data from the dies;

compare the data written to the dies with the data read from the dies; and

provide an error indication if the data written to the dies is not the same as the data read from the dies.

7. The method of processing and of testing a semiconductor wafer of claim 1 further comprising patterning the wafer to provide permanent Vcc and permanent Vss pads on the individual dies, and patterning the wafer to provide sacrificial Vcc and Vss pads associated with the dies, the respective permanent and sacrificial pads being connected relative to one another in parallel, the Vcc bus connecting with the sacrificial Vcc pads, the Vss bus connecting with the sacrificial Vss pads.

8. The method of processing and of testing a semiconductor wafer of claim 7 further comprising patterning the wafer to provide the sacrificial Vcc and Vss pads on individual dies.

9. The method of processing and of testing a semiconductor wafer of claim 1 wherein the step of providing die test cycling circuitry comprises providing individual test cycling circuitry on the individual dies, a cycling test pad being associated with the individual test cycling circuitry and being provided on the individual dies and being engaged by the Vcc bus;

the method further comprising;

patterning the wafer to provide permanent Vcc and permanent Vss pads on the individual dies, and patterning the wafer to provide sacrificial Vcc and Vss pads on the individual dies, the respective permanent and sacrificial pads being connected relative to one another in parallel on the individual dies, the Vcc bus connecting with the individual die sacrificial Vcc pads, the Vss bus connecting with the individual die sacrificial Vss pads.

10. The method of processing and of testing a semiconductor wafer of claim 1 further comprising patterning the conductive layer to provide fuses between the Vcc bus and individual Vcc pads.

11. The method of processing and of testing a semiconductor wafer of claim 1 further comprising patterning the wafer to provide permanent Vcc and permanent Vss pads on the individual dies, and patterning the wafer to provide sacrificial Vcc and Vss pads associated with the dies, the respective permanent and sacrificial pads being connected relative to one another in parallel, the Vcc bus connecting with the sacrifical Vcc pads, the Vss bus connecting with the sacrificial Vss pads, the conductive layer being patterned to provide fuses between the Vcc bus and the sacrificial Vcc pads.

12. The method of processing and of testing a semiconductor wafer of claim 1 wherein the step of providing die test cycling circuitry comprises providing individual test cycling circuitry on the individual dies, a cycling test pad being associated with the individual test cycling circuitry and being provided on the individual dies and being engaged by the Vcc bus;

the method further comprising;

patterning the wafer to provide permanent Vcc and permanent Vss pads on the individual dies, and patterning the wafer to provide sacrificial Vcc and Vss pads on the individual dies, the respective permanent and sacrificial pads being connected relative to one another in parallel on the individual dies, the Vcc bus connecting with the individual die sacrificial Vcc pads, the Vss bus connecting with the individual die sacrificial Vss pads, the conductive layer being patterned to provide fuses between the Vcc bus and the sacrificial Vcc pads.

13. The method of processing and of testing a semiconductor wafer of claim 1 wherein the step of etching the Vcc bus and Vss bus from the wafer is conducted without any prior photomaking of the Vcc buss and Vss bus.