Method for fabricating stacks of IC chips by segmenting a larger stack

• US 5,279,991 A
• Filed: 12/24/1992
• Issued: 01/18/1994
• Est. Priority Date: 05/15/1992
• Status: Expired due to Term

• Current Assignee: Aprolase Development Co LLC (Intellectual Ventures LLC)
• Original Assignee: Irvine Sensors Corp.
• Inventors: Pepe, Angel A., Minahan, Joseph A.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US07/996,794
• Time in Patent Office: 390 Days
• Field of Search: 437/208, 437/249, 437/915
• US Class Current: 438/109
• CPC Class Codes: H01L 21/67121 Apparatus for making assemblies not otherwise provided for, e.g. package constructions
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for fabricating stacks of IC chips into modules providing high density electronics. A relatively large number of layers are stacked, and then integrated by curing adhesive applied between adjacent layers. A large stack is formed, various processing steps are performed on the access plane face of the large stack, and then the large stack is segmented to form a plurality of smaller, or short, stacks. Means are provided for causing separation of the larger stack into smaller stacks, without disturbing the adhesive which binds the layers within each small stack.

Claims

1. A method for forming a stack containing IC chips for use as a dense electronic package having an access plane surface, which method comprises:

forming a large stack containing a large number of IC chips, each of which chips includes both integrated circuitry and a multiplicity of electrical leads extending from such circuitry to the same edge of the chip;

performing processing steps on the large stack to prepare the chip leads for connection to elements in an electronic system; and

separating the large stack into a plurality of small stacks, each of which constitutes a module for use in an electronic system.

2. The method of claim 1 in which the chips are formed of semiconductor material, and the processing steps performed on the large stack include:

etching one face of the large stack to cause the electrical leads thereon to extend beyond the face of the stack;

applying passivation material to the etched face of the large stack, thereby covering the semiconductor chip material;

removing sufficient passivation material to expose the ends of the electrical leads on the face of the large stack; and

applying lead-contacting metalization to the face of the large stack.

3. The method of claim 1 in which:

adhesive material of a first type is included in the large stack between each pair of adjacent chips intended for a given small stack; and

adhesive material of a second type is included between adjacent chips in the large stack which will be separated from one another to provide the short stacks.

4. The method of claim 3 in which the adhesive material of the first type is more resistant to elevated temperatures than the adhesive material of the second type, and the stack separating process comprises:

heating the large stack to a temperature at which the adhesive material of the second type is weakened; and

exerting a shearing force which causes the weakened adhesive material to give way.

5. The method of claim 1 in which:

the large stack is mounted in a retaining fixture; and

the access plane surface of the large stack is lapped by abrasive material carried on a rotating wheel.

6. The method of claim 1 in which:

a thin layer of material is removed from the access plane surface of the large stack by an etching process.

7. The method of claim 6 in which:

the large stack is supported inside a sealed chamber; and

material is removed from the access plane surface of the large stack by plasma etching within the sealed chamber.

8. The method of claim 6 in which:

material is removed from the access plane surface of the large stack by dipping it into a liquid etching material.

9. The method of claim 1 in which:

the large stack is mounted in a rotating spinner; and

passivation material placed on the access plane surface of the large stack is caused by spinner rotation to be spread by centrifugal force over the surface of the stack.

10. The method of claim 1 in which:

the large stack is supported in a holding tool inside a sealed vacuum chamber; and

metalization is applied by a vacuum deposition process on the access plane surface of the large stack, said metalization having conductive engagement with the electrical leads extending from the integrated circuitry of the IC chips.

11. The method of claim 10 in which:

the vacuum deposition process for applying metalization is sputtering.

12. The method of claim 10 in which:

the vacuum deposition process for applying metalization is evaporation.

13. The method of claim 2 in which:

the large stack is mounted in a retaining fixture; and

the access plane surface of the large stack is lapped by abrasive material carried on a rotating wheel.

14. The method of claim 2 in which:

a thin layer of material is removed from the access plane surface of the large stack by an etching process.

15. The method of claim 2 in which:

the large stack is mounted in a rotating spinner; and

passivation material is applied to the access plane surface of the layer stack and then spread by spinner rotation.

16. The method of claim 2 in which:

the large stack is supported in a holding tool inside a sealed vacuum chamber; and

metalization is applied by vacuum deposition on the access plane surface of the large stack, said metalization having conductive engagement with the electrical leads extending from the integrated circuitry of the IC chips.

17. The method of claim 1 in which the large stack is formed by stacking individual layers, most of which are IC chips and some of which are not IC chips.

18. The method of claim 17 in which the layers in the large stack are so arranged that each small stack formed by segmentation has top and bottom layers which are not IC chips.

19. The method of claim 1 in which no adhesive is applied in the large stack between chips which constitute the end chips of adjacent small stacks.

20. The method of claim 19 in which:

the chips forming the large stack are supported in a special holding tool while the processing steps are being performed.

21. A method for forming a plurality of short stacks containing IC chip layers from a large stack of layers, which method comprises:

providing IC chip layers, each of which chips includes both integrated circuitry and a multiplicity of electrical leads extending from such circuitry to the same edge of the chip;

providing non-IC chip layers to serve as bottom and top layers of short stacks;

starting the large stack with a non-IC chip layer which is the bottom layer of a first small stack;

placing a plurality of IC chip layers above the bottom layer of the first small stack;

completing the first small stack with a top layer which is a non-IC chip layer;

starting a second small stack by adding to the large stack a non-IC chip layer which is the bottom layer of a second small stack;

placing a plurality of IC chip layers above the bottom layer of the second small stack;

completing the second small stack with a top layer which is a non-IC chip layer;

stacking IC chip layers and non-IC chip layers to provide a plurality of small stacks;

securing together with adhesive material all of the adjacent layers in a large stack;

said large stack having a planar access surface which contains the end of the electrical leads of the IC chip layers;

performing processing steps on the planar access surface of the large stack; and

thereafter segmenting the large stack to provide a plurality of individual small stacks.

22. The method of claim 21 in which:

permanent adhesive material is used between all adjacent layers within a given small stack; and

sacrificial adhesive material is used between the top layer of each small stack and the bottom layer of the next small stack.

23. The method of claim 21 in which the processing steps performed on the planar access surface of the large stack include:

applying passivation material to the planar access surface;

exposing the electrical leads on the planar access surface; and

applying metallization to the planar access surface, which is electrically connected to said electrical leads, and which provides electrical conduction from said leads to external circuitry.

24. A method for forming a plurality of short stacks containing IC chip layers from a large stack of layers, which method comprises:

providing IC chip layers, each of which chips includes both integrated circuitry and a multiplicity of electrical leads extending from such circuitry to the same edge of the chip;

providing non-IC chip layers to serve as bottom and top layers of short stacks;

starting the large stack with a non-IC chip layer which is the bottom layer of a first small stack;

placing a plurality of IC chip layers above the bottom layer of the first small stack;

completing the first small stack with a top layer which is a non-IC chip layer;

starting a second small stack by adding to the large stack a non-IC chip layer which is the bottom layer of a second small stack;

placing a plurality of IC chip layers above the bottom layer of the second small stack;

completing the second small stack with a top layer which is a non-IC chip layer;

stacking IC chip layers and non-IC chip layers to provide the a plurality of small stacks;

securing together with adhesive material all of the adjacent layers within a small stack, but not the top and bottom layers of adjacent small stacks;

said large stack having a planar access surface which contains the ends of the electrical leads of the IC chip layers;

performing processing steps on the planar access surface of the large stack; and

thereafter segmenting the large stack to provide a plurality of individual small stacks.