Method for testing semiconductor integrated circuits soldered to boards and use of a transistor tester for this method

• US 5,280,237 A
• Filed: 03/23/1992
• Issued: 01/18/1994
• Est. Priority Date: 03/30/1991
• Status: Expired due to Fees

• Current Assignee: Scorpion Technologies AG
• Original Assignee: ITA Ingenieurburo Fur Testaufgaben GmbH
• Inventors: Buks, Manfred
• Primary Examiner(s): NGUYEN, VINH P
• Application Number:
  US07/855,666
• Time in Patent Office: 666 Days
• Field of Search: 324/158 R, 324/73.1, 324/158 T, 371/22.6, 371/22.1, 371/15.1, 371/24, 357/41, 437/8, 257/48, 257/40
• US Class Current: 324/762.02
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence
• CPC Class Codes: G01R 31/70 Testing of connections between components and printed circuit boards G01R31/68 takes precedence

Abstract

A method for testing a semiconductor integrated circuit soldered into a printed circuit board makes use of the existence of parasitic transistors which occur on integrated circuits having diodes formed thereon. The method includes applying a voltage across the pins of the integrated circuit to be tested, measuring currents resulting from the voltage applied across the pins of the integrated circuit, connecting a transistor tester to selected pins of the integrated circuit, and determining typical control or switching characteristics of a parasitic transistor (1T, 2T) of the semiconducting integrated circuit (IC1, IC2). A commercial transistor tester is usable to perform the method.

Claims

1. A method of testing an integrated circuit comprising the steps of

determining the existence of parasitic transistors in an integrated circuit of a first type while the integrated circuit is unattached to a circuit board by ascertaining diode characteristics of combinations of two pins at a time,

connecting a transistor tester to selected pins of the integrated circuit,

applying a voltage across the pins of an integrated circuit of said first type with the transistor tester while said integrated circuit is soldered to a circuit board,

measuring the currents resulting from the voltage applied across the pins of the integrated circuit, and

determining from the measured currents control characteristics of a parasitic transistor of the integrated circuit using the tester.

2. A method for testing a semiconductor integrated circuit having a plurality of pins soldered to a circuit board comprising the steps of

selecting a set of three pins of the integrated circuit of which one is a ground pin of the integrated circuit and the other two are non-ground pins,

connecting a non-ground pin of said set to a ground connection of a transistor tester,

connecting the other non-ground pin of the set to a first output of the tester providing a first voltage, the first voltage being selected to draw current from the collector of a conducting transistor,

connecting the ground pin of the set to a second output of the tester delivering a second voltage, the second voltage being of a value selected to cause a transistor to become conductive when applied between its base and emitter electrodes, and

determining whether the part of the integrated circuit connected to the set of selected pins of the integrated circuit responds to the voltages in the way a conductive transistor would respond.

3. A method according to claim 2 wherein the transistor tester is a commercial transistor tester.

4. A method according to claim 2 and including

connecting the tester to a different set of three pins and repeating the steps of applying voltage, measuring current and determining characteristics.

5. A method according to claim 4 and including the steps of connecting, applying voltage, measuring current and determining characteristics with different sets of three pins until all permutations of sets of three pins of the integrated circuit have been tested.