DC integrating display driver employing pixel status memories

• US 5,280,280 A
• Filed: 05/24/1991
• Issued: 01/18/1994
• Est. Priority Date: 05/24/1991
• Status: Expired due to Term

• Current Assignee: Positive Technologies
• Original Assignee: Robert Hotto
• Inventors: Hotto, Robert
• Primary Examiner(s): BRIER, JEFFERY A
• Application Number:
  US07/705,190
• Time in Patent Office: 970 Days
• Field of Search: 340/701, 340/784, 340/812, 340/811, 340/793, 340/719, 340/765
• US Class Current: 345/94
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0278 Details of driving circuits arranged to drive both scan and data electrodes
• CPC Class Codes: G09G 2320/0204 Compensation of DC component across the pixels in flat panels
• CPC Class Codes: G09G 2320/041 Temperature compensation
• CPC Class Codes: G09G 2340/16 Determination of a pixel data signal depending on the signal applied in the previous frame
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/2007 Display of intermediate tones
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3629 using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
• CPC Class Codes: G09G 3/3651 using multistable liquid crystals, e.g. ferroelectric liquid crystals

Abstract

This invention relates to an improved drive and control means for matrix addressable electro-optic displays, such as passive matrix LCDs and active matrix LCDs. The present invention achieves improved drive and control of displays through the use of real time computation and memory circuits to simulate the electro-optic condition and the accumulated DC bias of individual display elements. This eliminates the burden of frequent and symmetrical reversals of the drive polarity, and allows the implementation of flexible DC drive methodologies.

Claims

1. A system for displaying a demanded image in an array of pixels, wherein said array of pixels is driven to produce said demanded image, wherein said pixels operate within a range of controllable driven gray levels, the gray level displayed by each of said pixels responsive to electric fields applied to each of said pixels;

said system comprising;

memory means for storing electro-optic conditions of pixels in said array;

driver means for applying drive signals to selective pixels; and

means for controlling the level of said drive signals applied to a pixel responsive to the demanded image and to the stored electro-optic condition existing on said pixel.

2. A system as set forth in claim 1, wherein said display comprises a matrix array of rows and columns of pixels.

3. A system as set forth in claim 2, wherein said driver means comprises means for selectively applying said drive signals to any of said pixels in the matrix array.

4. A system as set forth in claim 3, wherein at least a plurality of said pixels exhibit a maximum bias violation tolerances, each of said pixels during operation accumulating a DC bias level thereon, said system comprises means for comparing said MVBT of said pixels with the accumulated DC bias levels existing on said pixels.

5. A system as set forth in claim 3, wherein:

said memory means comprises means for storing a representation of the existing electro-optic condition of said pixels to simulate said display and demanded image means for generating demanded signals representative of the demanded image display sought on said array of pixels;

said controlling means comprises a microprocessor connected to said storing means and said demanded image means of said memory means for comparing said demanded image signals with said representation of existing electro-optic condition of said pixels and for generating control signals in response to said comparing, said control signals being supplied by said microprocessor to said driver means to produce said drive signals for said pixels.

6. A system as set forth in claim 4, wherein:

said memory means comprises means for storing a representation of the existing electro-optic condition of said pixels to simulate said display nd demanded image means for generating demanded signals representative of the demanded image display sought on said array of pixels;

said controlling means comprises a microprocessor connected to said storing means and said demanded image means of said memory means for comparing said demanded image signals with said representation of existing electro-optic condition of said pixels and for generating control signals in response to said comparing, said control signals being supplied by said microprocessor to said driver means to produce said drive signals for said pixels.

7. A system as set forth in claim 5, further comprising ambient signals means responsive to the environment of said array of pixels, said ambient signal means being connected to said microprocessor to adjust said control signals.

8. A system as set forth in claim 7, wherein the ambient signal means is responsive to the environmental temperature of the array of pixels.

9. A system as set forth in claim 7, wherein the ambient signal means is responsive to the ambient light conditions of said array of pixels,

10. A system as set forth in claim 4, wherein said system comprises means for identifying the pixel in the greatest danger of reaching said maximum bias violation tolerance.

11. A system as set forth in claim 4, wherein said system comprises means for reversing the polarity of the driver signals upon detection that a pixel is about to reach the maximum bias violation tolerance.

12. A system as set forth in claim 10, wherein said system comprises means for reversing the polarity of the driver signals upon detection that a pixel is about to reach the maximum bias violation tolerance.

13. A system as set forth in claim 1, wherein the sequence of driving the array of pixels is responsive to the existing electro-optic conditions on said pixels.

14. A system as set forth in claim 5, wherein said control signal produced for driving a pixel by said microprocessor is responsive to the gray level appearing on proximately located pixels.

15. A system as set forth in claim 1, wherein said drive signal is controllable to be at any level within the amplitude of the range of voltage levels which can be applied to the pixels.

16. A system as set forth in claim 5, wherein said drive signal is controllable to be at any level within the amplitude of the range of voltage levels which can be applied to the pixels.

17. A system as set forth in claim 6, wherein said drive signal is controllable to be at any level within the amplitude of the range of voltage levels which can be applied to the pixels.

18. A system as set forth in claim 1, wherein said means for controlling said drive signals comprises means for varying the frequency of the drive signal applied to individual pixels.

19. A system as set forth in claim 5, wherein said means for controlling said driver signals comprises means for varying the frequency of the drive signal applied to individual pixels.

20. A system as set forth in claim 6, wherein said means for controlling said drive signals comprises means for varying the frequency of the drive signal applied to individual pixels.

21. A system as set forth in claim 1, wherein said pixels are located between at least a single backplane and a single segment plane for their excitation, said driver means comprises means for selectively interchanging the function of the backplane with the function of the segment plane.

22. A system as set forth in claim 21, wherein the selective interchanging of the functions of segment plane and backplane is controlled in real time.

23. A system as set forth in claim 1, wherein said pixels are located between a plurality of backplanes and a plurality of segment planes for their excitation, said river means comprises means for simultaneously driving at least two of said backplanes.

24. A system as set forth in claim 5, wherein said pixels are located between a plurality of backplanes and a plurality of segment planes for their excitation, said driver means comprises means for simultaneously driving at least two of said backplanes.

25. A system as set forth in claim 6, wherein said pixels are located between a plurality of backplanes and a plurality of segment planes for their excitation, said driver means comprises means for simultaneously driving at least two of said backplanes.

26. A system as set forth in claim 1, wherein said controlling means comprises means for generating a difference image array in said memory means corresponding to the differences between said demanded image and the existing electro-optic condition on said pixels.

27. A system as set forth in claim 26, wherein said means for generating a difference image array operates on a real time basis.

28. A system as set forth in claim 5, wherein said microprocessor in response to said comparing of said demanded image with the existing electro-optic condition on said pixels is operable to generate a difference image array in said memory means corresponding to the differences between said demanded image and the existing electro-optic condition on said pixels.

29. A system as set forth in claim 28, wherein said means for generating a difference image array operates on a real time basis.

30. A system as set forth in claim 1, wherein said means for applying a drive signal to selective pixels comprises means for driving said pixels in a sequence responsive to said pixels requiring the next largest drive signal to produce said demanded image.

31. A system as set forth in claim 1, wherein said memory means stores a representation of the net accumulated DC bias level of said pixels.

32. A system as set forth in claim 1, wherein said pixels comprise active matrix displays.

33. A system as set forth in claim 32, wherein said active matrix display comprises a plurality of addressable active devices, said driver means being operable to drive different selected ones of said addressable active devices in opposite polarities concurrently.

34. A system as set forth in claim 33, wherein different ones of said addressable active devices can be selectively driven or discharged concurrently.

35. A system as set forth in claim 33, wherein said addressable active devices are subjected to bias reconciliation, wherein the bias reconciliation of each of said addressable active devices is controllable independent of other elements of said display.

36. A system as set forth in claim 32, wherein said memory means stores a representation of the net accumulated DC bias level of said pixels, and the net accumulated DC bias level of said addressable active devices is accumulated independently.

37. A system as set forth in claim 1, wherein said pixels comprise active matrix LCD displays.

38. A system as set forth in claim 5, wherein said means for applying a drive signal to selective pixels comprises means for driving said pixels in a sequence responsive to said pixels requiring the next largest drive signal to produce said demanded image.

39. A system as set forth in claim 1, wherein said pixels comprise passive matrix displays.

40. A driver system to drive a plurality of liquid crystal display pixels which produce a demanded display image, said driver system comprising:

means for storing a representation of the existing electro-optic condition of a plurality of liquid crystal display pixels;

means for comparing said demanded display image and said representation of the existing electro-optic condition of individual pixels of said plurality of pixels and for producing drive signals, the level of said drive signal being dependent on the difference between said demanded display image and said representation of the existing electro-optic condition of each pixel; and

means for receiving and applying said drive signals to drive said pixels to produce said demanded display image in a sequence responsive to the representation of the electro-optic conditions of individual pixels of said plurality of pixels.

41. A system as set forth in claim 40, wherein said plurality of pixels are arranged in rows and columns.

42. A system as set forth in claim 40, wherein each of said pixels has a maximum bias violation tolerance, said driver system comprising means for reversing the polarity of said drive signals upon determining that any of said pixels shall approach said maximum bias violation tolerance thereof.

43. A system as set forth in claim 40, wherein each of said pixels has a maximum bias violation tolerance, said driver system comprising means for reversing the polarity of said drive signals prior to any of said pixels reaching said maximum bias violation tolerance thereof.

44. A system as set forth in claim 40, wherein the sequence of driving said pixels is responsive to the required level of drive signal for said pixels.

45. A system as set forth in claim 40, wherein said means for storing a representation of the existing electro-optic condition and said means for comparing said representation to said demanded display image operate in real time.

46. A system as set forth in claim 40, wherein said system further comprises means for storing the bias voltage history of said pixels.

47. A system as set forth in claim 40, wherein said liquid crystal display pixels are connected to a plurality of backplanes, said driver system comprising means for simultaneously driving a plurality of said backplanes.

48. A system as set forth in claim 40, wherein said driver system drives said pixels in real time.

49. A system as set forth in claim 48, wherein said driver system drives said pixels asynchronously.

50. A system as set forth in claim 49, wherein said pixels comprise an active matrix display.

51. A system as set forth in claim 40, wherein said liquid crystal display is an active matrix liquid crystal display.

52. A system as set forth in claim 51, wherein said active matrix liquid crystal display comprises a plurality of addressable active devices, said driver system being operable to drive different selected ones of said addressable active devices in opposite polarities concurrently.

53. A system as set forth in claim 52, wherein different ones of said addressable active devices can be selectively driven or discharged concurrently.

54. A system as set forth in claim 52, wherein said addressable active devices are subjected to bias reconciliation, wherein the bias reconciliation of each of said addressable active devices is controllable independent of other elements of said display.

55. A system as set forth in claim 40, wherein liquid crystals display is a passive matrix liquid crystal display.

56. A system for producing a demanded image on a plurality of pixels, wherein said pixels can produce desired gray levels, said system comprising:

simulation means for simulating the existing electro-optic condition of said pixels; and

means responsive to said simulation of the existing electro-optic condition of said pixels and to a demanded image for producing drive signals for said pixels to produce said demanded image.

57. A system as set forth in claim 56, wherein said simulation means comprises means for identifying the location of each pixel with respect to each other of said plurality of pixels.

58. A system as set forth in claim 56, wherein the pixels are defined by a plurality of electrodes arrayed in rows and columns, said system further comprising means for selectively driving said pixels by driving said row and column electrodes.

59. A system as set forth in claim 58, wherein said row and column electrodes are driven sequentially.

60. A system as set forth in claim 58, wherein said row and column electrodes are driven asequentially.

61. A drive and control apparatus for matrix addressable electro-optic displays formed of a plurality of individual pixels, said drive and control apparatus comprising:

memory means for simulating the existing electro-optic condition on said pixels on a pixel by pixel basis;

demanded image means for producing pixel by pixel demanded electro-optic conditions; and

real time control means for driving each of said pixels by a drive signal level related to the specific simulated and demanded electro-optic conditions on said pixel.

62. Apparatus as set forth in claim 61, wherein said pixels comprise liquid crystal display elements, each of which has a maximum accumulated DC bias level above which DC bias level the liquid crystal display element should not be subjected, said apparatus further comprising means for controlling the DC bias level conditions on said liquid crystal display elements and means for applying DC control techniques to drive said picture elements to produce said demanded image.

63. A drive system for matrix addressable electro-optic displays formed of a plurality of pixels, said pixels being driven to product display contrast, the display contrast being expressable in gray levels, said drive system comprising:

means for applying DC power in the form of plurality of pulses to said pixels to produce the desired display contrast level; and

means for selecting the value of said DC power level at any level between its minimum and maximum applied values by selecting the order and sequence of said pulses applied to said pixels.

64. A system as set forth in claim 63, wherein said gray levels comprise a plurality of bands of gray levels, said drive means being operable for maintaining said pixels in selected gray bands during the display operation.

65. A system as set forth in claim 64, wherein drive system applies drive signals to said pixels in real time.

66. A system as set forth in claim 63, wherein the value of said DC power comprises DC voltage.

67. A system as set forth in claim 66, wherein the value of said DC power comprises the DC voltage and the time during which it is applied to said pixels.

68. A drive system for a matrix addressable electro-optic display formed of a plurality of pixels for producing a display image, wherein said image is produced during successive display periods, said pixels capable of being driven in either of two polarity directions to produce a desired display image, said drive system comprising:

memory means for storing the existing DC bias level on said pixels in the form of a representation of the accumulated DC bias levels on said pixels during successive display periods and for producing a drive signal having the same polarity as that of the existing bias level; and

means for receiving said drive signal and driving said pixels in one polarity for a plurality of successive display periods.

69. A system as set forth in claim 68, wherein said memory means comprises means to derive DC bias violation values relating to the existing bias levels and the time of existence of said bias levels on said pixels.