Charge pump which operates on a low voltage power supply

• US 5,280,420 A
• Filed: 10/02/1992
• Issued: 01/18/1994
• Est. Priority Date: 10/02/1992
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Rapp, A. Karl
• Primary Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US07/955,939
• Time in Patent Office: 473 Days
• Field of Search: 363/59, 363/60, 307/109, 307/110
• US Class Current: 363/60
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/076 the clock signals being boosted to a value being higher than the input voltage value

Abstract

A charge pump for increasing the amplitude of a voltage supply signal is disclosed. The charge pump includes an auxiliary pump, a buffer stage, and a main pump. The auxiliary pump generates several intermediate voltage signals in response to a pair of complementary clock signals. Each intermediate voltage signal has a different amplitude which is greater than the amplitude of the voltage supply signal. The buffer stage increases the amplitudes of the pair of complementary clock signals in response to the several intermediate voltage signals generated by the auxiliary pump. The main pump increases the amplitude of the voltage supply signal in response to the pair of increased amplitude complementary clock signals generated by the buffer stage.

Claims

1. A charge pump for increasing the amplitude of a voltage supply signal, the charge pump comprising:

an auxiliary pump that is connected to receive the voltage supply signal and that responds to a first and a second complementary clock signals by generating a plurality of intermediate voltage signals, each of the intermediate voltage signals having a different amplitude which amplitude is greater than the amplitude of the voltage supply signal;

buffer means for increasing the amplitudes of the first and second complementary clock signals in response to the plurality of intermediate voltage signals; and

a main pump that increases the amplitude of the voltage supply signal in response to the first and second increased amplitude complementary clock signals.

2. The charge pump of claim 1, wherein the buffer means comprises:

a plurality of series-connected first inverters responsive to the first complementary clock signal, each of the first inverters being powered by a corresponding one of the plurality of intermediate voltage signals; and

a plurality of series-connected second inverters responsive to the second complementary clock signal, each of the second inverters being powered by a corresponding one of the plurality of intermediate voltage signals.

3. The charge pump of claim 2, wherein the buffer means further comprises:

a plurality of filter capacitors, each filter capacitor being coupled between a different one of the plurality of intermediate voltage signals and ground potential.

4. The charge pump of claim 2, wherein the first and second inverters comprise CMOS inverters.

5. The charge pump of claim 1, wherein the auxiliary pump comprises:

a plurality of series-connected diode means for providing unidirectional conduction, each of the diode means having an anode; and

a plurality of capacitor means for storing electric charge, each of the capacitor means being coupled between one of the complementary clock signals and the anode of one of the diode means.

6. The charge pump of claim 5, wherein:

each of the diode means comprises a diode-connected transistor; and

each of the capacitor means comprises a capacitor-connected transistor.

7. The charge pump of claim 1, wherein the main pump comprises:

a plurality of series-connected diode means for providing unidirectional conduction, each of the diode means having an anode; and

a plurality of capacitor means for storing electric charge, each of the capacitor means being coupled between one of the increased amplitude complementary clock signals and the anode of one of the diode means.

8. The charge pump of claim 7, wherein:

each of the diode means comprises a diode-connected transistor; and

each of the capacitor means comprises a capacitor-connected transistor.

9. A charge pump for increasing the amplitude of a voltage supply signal, the charge pump comprising:

a plurality of auxiliary pump stages for generating a plurality of intermediate voltage signals having different amplitudes which amplitudes are all greater than the amplitude of the voltage supply signal, each of the plurality of auxiliary pump stages being responsive to at least one of a pair of complementary clock signals;

a plurality of first buffers for increasing the amplitude of one of the complementary clock signals, each of the first buffers being responsive to a different one of the plurality of intermediate voltage signals;

a plurality of second buffers for increasing the amplitude of the other complementary clock signal, each of the second buffers being responsive to a different one of the plurality of intermediate voltage signals; and

a plurality of main pump stages for increasing the amplitude of the voltage supply signal, each of the plurality of main pump stages being responsive to at least one of the increased amplitude complementary clock signals generated by the first and second buffer means.

10. The charge pump of claim 9, further comprising:

a plurality of filter capacitors, each filter capacitor being coupled between a different one of the plurality of intermediate voltage signals and ground potential.

11. The charge pump of claim 9, wherein:

the plurality of first buffers comprises a plurality of series-connected first CMOS inverters, each of the first CMOS inverters being powered by a different one of the plurality of intermediate voltage signals; and

the plurality of second buffers comprises a plurality of series-connected second CMOS inverters, each of the second CMOS inverters being powered by a different one of the plurality of intermediate voltage signals.

12. The charge pump of claim 9, wherein each of the auxiliary pump stages comprises:

a diode means for providing unidirectional conduction, the diode means having an anode and a cathode; and

a capacitor means for storing electric charge, the capacitor means being coupled between the anode of the diode means and one of the complementary clock signals.

13. The charge pump of claim 12, wherein:

the diode means comprises a diode-connected transistor; and

the capacitor means comprises a capacitor-connected transistor.

14. The charge pump of claim 9, wherein each of the plurality of main pump stages comprises:

a diode means for providing unidirectional conduction, the diode means having an anode and a cathode; and

a capacitor means for storing electric charge, the capacitor means being coupled between the anode of the diode means and one of the increased amplitude complementary clock signals.

15. The charge pump of claim 14, wherein:

the diode means comprises a diode-connected transistor; and

the capacitor means comprises a capacitor-connected transistor.

16. A charge pump for increasing the amplitude of a voltage supply signal, the charge pump comprising:

an auxiliary pump having a plurality of series-connected auxiliary pump stages for generating a plurality of intermediate voltage signals, each of the intermediate voltage signals having a different amplitude which amplitude is greater than the amplitude of the voltage supply signal, each of the auxiliary pump stages being responsive to at least one of a pair of complementary clock signals;

a plurality of series-connected first inverters for increasing the amplitude of one of the complementary clock signals, each of the first inverters being powered by a different one of the plurality of intermediate voltage signals;

a plurality of series-connected second inverters for increasing the amplitude of the other complementary clock signal, each of the second inverters being powered by a different one of the plurality of intermediate voltage signals; and

a main pump having a plurality of series-connected main pump stages for increasing the amplitude of the voltage supply signal, each of the main pump stages being responsive to at least one of the increased amplitude complementary clock signals.

17. The charge pump of claim 16, further comprising:

a plurality of filter capacitors, each filter capacitor being coupled between a different one of the plurality of intermediate voltage signals and ground potential.

18. The charge pump of claim 16, wherein the first and second inverters comprise CMOS inverters.

19. The charge pump of claim 16, wherein each of the auxiliary pump stages comprises:

a diode-connected transistor; and

a capacitor-connected transistor coupled between the drain of the diode-connected transistor and one of the complementary clock signals.

20. The charge pump of claim 16, wherein each of the main pump stages comprises:

a diode-connected transistor; and

a capacitor-connected transistor coupled between the drain of the diode-connected transistor and one of the increased amplitude complementary clock signals.