High speed fail processor

• US 5,280,486 A
• Filed: 02/08/1993
• Issued: 01/18/1994
• Est. Priority Date: 03/16/1990
• Status: Expired due to Term

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Reichert, Peter A., Arkin, Brian J., Brown, Benjamin J.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US08/015,070
• Time in Patent Office: 344 Days
• Field of Search: 371/29.1, 371/16.5, 371/21.6, 371/22.6, 395/575
• US Class Current: 714/45
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory

Abstract

An apparatus for processing failure information received from a node of a circuit under test. The apparatus includes a fail processor which receives test data from a node and generates failure data based upon the test data, a plurality of fail memories, each memory being configured to receive and store certain fail data, and a sequence memory configured-to store sequence information indicating in what order the failure data is stored in the plurality of fail memories.

Claims

1. Apparatus for testing a node of a circuit under test comprising

a high-speed formatter including means for generating a high-speed test signal for application to a driver connected to said node in response to test pattern information received from a pattern generator, means for receiving a high-speed detected test signal from a detector connected to said node, and means for generating two half-speed detected test signals that contain alternate cycles of said high-speed detected test signal,

first and second fail processor means connected to said high-speed formatter to receive respective half-speed detected signals for generating and outputting failure information based upon the states of cycles of said half-speed detected test signals,

said failure information outputted by a particular fail processor means relating to specific, but not necessarily all, cycles of its respective half-speed detected test signal,

first and second fail memory means connected to respective said first and second fail processor means for receiving said failure information from respective said fail processor means and for storing said failure information for specific cycles received from said fail processor means in successive memory locations, and

sequence means for storing information indicating the sequence in which failure information is stored in said first and second fail memory means.

2. The apparatus of claim 1 wherein said sequence means stores said information indicating the sequence as said first and second fail memory means store said failure information.

3. The apparatus of claim 1 wherein said sequence means comprises first and second sequence memory means associated with respective said first and second memory means, said sequence means storing sequence bits in said sequence memory means associated with said failure information for specific cycles, said sequence bits indicating whether the previously stored failure information is stored in the same fail memory means or not.

4. The apparatus of claim 3 wherein said sequence means stores a single sequence bit for failure information for a specific cycle.