Circuit arrangement for removing stuff bits

• US 5,280,502 A
• Filed: 10/25/1991
• Issued: 01/18/1994
• Est. Priority Date: 11/08/1990
• Status: Expired due to Fees

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Robledo, Miguel, Niegel, Michael, Urbansky, Ralph
• Primary Examiner(s): Kuntz, Curtis
• Assistant Examiner(s): VO, DON NGUYEN
• Application Number:
  US07/782,710
• Time in Patent Office: 816 Days
• Field of Search: 375/112, 375/117, 375/118, 370/102, 370/84, 370/99, 370/108, 370/101, 370/105.1, 341/61, 341/95
• US Class Current: 375/363
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Abstract

The described circuit arrangement for removing stuff bits from a frame-structured signal which is available in n parallel bits, comprises a memory circuit (2) which is supplied with the parallel bits (1b). The memory circuit (2) is followed by a controllable selection circuit (3) having n outputs (3a). A control circuit (9) produces control signals (9b, 9c), which determine which bits stored in the memory circuit are transported to the n outputs (3a) of the selection circuit (3). The memory circuit (2) comprises only n delay elements by which each of the n parallel bits (1b) is delayed for the duration of one bit. So as to provide that n delay elements will be sufficient, the control circuit (9) is to block at predetermined time intervals the acceptance of new bits in one or a plurality of delay elements.

Claims

1. Circuit arrangement for removing stuff bits from a frame-structured signal, which is available as sequences of n bits supplied in parallel, comprising

a) a memory circuit (2) for storing the n bits supplied in parallel,

b) a controllable selection circuit (3) having n outputs and coupled to the output of the memory circuit (2) , and

c) a control circuit (9) having a control signal for determining a switching state of the selection circuit (3), the switching state determining which of the bits stored in the memory circuit (2) are applied to the n outputs of the selection circuit, characterized in that

d) the memory circuit comprises n delay elements for delaying each of the n bits supplied in parallel for a duration of one bit,

e) at predetermined intervals, the control circuit blocks acceptance of new bits in up to p-1 delay elements out of the n delay elements, where p represents a maximum number of stuff bits that can occur simultaneously among the n bits supplied in parallel, and p≦

n.

2. Circuit arrangement as claimed in claim 1, characterized in that the following features are implemented:

f) the selection circuit (3) comprises cascades of addressable multiplexers,

g) the control circuit comprises a modulo-n counting stuff bit counter (9) whose count can be adjusted by means of a negative justification signal (9a),

h) the count (9b of the stuff bit counter (9) as well as the negative justification signal (9b) form addresses for the multiplexers, and

i) the address inputs of the multiplexers of a cascade are arranged in parallel.