Memory access control system for use with a relatively small size data processing system

• US 5,280,589 A
• Filed: 04/22/1991
• Issued: 01/18/1994
• Est. Priority Date: 07/30/1987
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakamura, Nobutaka
• Primary Examiner(s): RUDOLPH, REBECCA
• Application Number:
  US07/689,720
• Time in Patent Office: 1,002 Days
• Field of Search: 395/250, 395/325, 395/400, 395/425
• US Class Current: 710/52
• CPC Class Codes: G06F 13/285 Halt processor DMA G06F13/30 takes precedence

Abstract

A memory access control system is disclosed. In this system, a CPU, a low speed memory, a high speed memory and direct memory access controller (DMAC) are connected to a system bus. A high speed memory is connected through a local bus to the CPU. A control circuit is connected to the local bus, the system bus and the high speed memory. A bidirectional buffer is connected to the local and system buses. When the CPU accesses the high speed memory, the control circuit addresses the high speed memory and disables the buffer. As a result, data can directly be transferred between the CPU and the high speed memory. When the CPU accesses the low speed memory, the control circuit drives the system bus according to a protocol of the system bus, thereby to address the low speed memory and enables the buffer. As a result, data can be transferred between the CPU and the low speed memory, via a route of the local bus, the buffer and the system bus. When the DMAC accesses the high speed memory, the control circuit addresses the high speed memory and enables the buffer according to the system bus protocol. As a result, data can be transferred between the DMAC and the high speed memory, through a route of the local bus, the buffer, and the system bus. When the DMAC accesses the low speed memory, the control circuit disables the high speed memory and the buffer.

Claims

1. A data processing system having a single processor and compatible with a system-bus system, comprising:

a local bus including a local address/control bus and a local data bus;

a system bus including a system address/control bus and a system data bus;

a high speed memory coupled to the local data bus;

a low speed memory coupled to the system data bus;

a direct memory access controller (DMAC) coupled to the system bus;

a central processing unit (CPU) coupled to the local address/control bus and local data bus;

an input/output device coupled to the system bus;

gate means for selectively coupling the local data bus and the system data bus; and

memory control means, directly connected to the high speed memory, the local address/control bus, and the system address/control bus, for detecting a device requesting a memory access and a data-transmission route, in response to the data on the system address/control bus and the local address/control bus, for supplying an address and address control signals to the high speed memory, thereby controlling and driving the high speed memory to transfer data via the local data bus when the CPU accesses the high speed memory, for supplying an address and address control signals to the high speed memory, thereby controlling and driving the high speed memory and the gate means to transfer data via the local data bus, the gate means, and the system data bus when the input/output device accesses the high speed memory by means of the DMAC and said local bus is coupled to said system bus through said gate means, and for controlling the gate means to coupled the local data bus and the system data bus when the CPU accesses the low speed memory.

2. The data processing system according to claim 1, wherein the gate means couples the local bus to the system bus when the device accesses the memory through the gate means and decouples the local bus from the system bus when the CPU accesses the memory.

3. The system according to claim 1, wherein said DMAC outputs a request signal to the CPU when requesting access to the memory, said CPU outputs an acknowledge (ACK) signal to the DMAC in response to the request signal, and said control means, in response to the ACK signal, detects that the input/output device is accessing the memory by means of the DMAC.

4. A data processing system having a single processor and compatible with a system-bus system, comprising:

a local bus including a local address/control bus and a local data bus;

a system bus including a system address/control bus and a system data bus whose bus cycle is lower than that of said local bus;

a high speed memory coupled to the local data bus;

a low speed memory coupled to the system bus;

a device coupled to the system bus;

a direct memory access controller (DMAC) coupled to the system bus;

a central processing unit (CPU) coupled to the local bus;

gate means for coupling the local data bus to the system data bus when the CPU accesses the low speed memory or the device accesses the high speed memory by means of the DMAC and for decoupling the local data bus from the system data bus when the CPU accesses the high speed memory or the device accesses the low speed memory by means of the DMAC; and

memory control means, connected to the high speed memory, the local address/control bus, and the system address/control bus, for detecting a memory to be accessed and a device requesting memory access and a data-transmission route, in response to data on the system address/control bus and the local address/control bus, for suppling an address and address control signals to the high speed memory, thereby controlling the high speed memory to transfer data via the local data bus when the CPU accesses the high speed memory, for supplying an address and address control signals to the high speed memory, thereby controlling the high speed memory to transfer data via the local bus, the gate means, and the system bus when the device accesses the high speed memory through the gate means by means of the DMAC and said local data bus is coupled to said system data bus through said gate means, for synchronizing the control and address data on the local address/control bus of the system bus, for transmitting the synchronized control and address data to the system address/control bus, and for connecting the local data bus and the system data bus through said gate means when the CPU accesses the low speed memory.

5. The system according to claim 4, wherein said DMAC outputs a request signal to the CPU when requesting access to the memory, said CPU outputs an acknowledge (ACK) signal to the DMAC in response to the request signal, and said control means, in response to the ACK signal, detects that the input/output device is accessing the memory by means of the DMAC.

6. A data processing system having a single processor and a compatibility with a single bus system, comprising:

a first bus including a first address/control bus and a first data bus;

a second bus including a second address/control bus and a second data bus;

a first memory coupled to the first data bus;

a second memory coupled to the second data bus;

a device coupled to the second bus;

a central processing unit (CPU) coupled to the first bus;

gate means for selectively coupling the first data bus and the second data bus; and

control means, directly coupled to the first memory, the first address/control bus, and the second address/control bus, for supplying an address and address control signals to the first memory, thereby driving the first memory to transfer data via the first data bus when the CPU accesses the first memory, and for supplying an address and address control signals to the first memory, thereby controlling the first memory and gate means to transfer data via the first bus, the gate means, and the second bus and to connect said first bus to said second bus through said gate means when the device accesses the first memory, and for synchronizing the control and address data on the first address/control bus with a bus clock of the second bus, transmitting the synchronized control and address data to the second address/control bus, and connecting the first data bus to the second data bus through said gate means when the CPU accesses the second memory.

7. A data processing system according to claim 6, further comprising a direct memory access controller (DMAC) coupled to the second bud, and wherein said DMAC outputs a request signal to the CPU when requesting access to the first memory, said CPU outputs an acknowledge (ACK) signal to the DMAC in response to the request signal, and said control means, in response to the ACK signal, detects that the input/output device is accessing the first memory by means of the DMAC.

8. A data processing system, comprising:

first bus means for transferring signals including first address/control bus means for transferring address/control signals and first data bus means for transferring data signals;

second bus means for transferring signals including second address/control bus means for transmitting address/control signals and second data bus means for transmitting data signals;

first memory means, coupled to the first data bus means, for storing data;

second memory means, coupled to the second data bus means, for storing data;

processing means, coupled to the first bus means, for accessing the first memory means;

input/output means coupled to the second bus means for accessing the first memory means;

gate means for selectively coupling the first data bus means and the second data bus means; and

control means, directly coupled to the first memory means, the first address/control bus means, and the second address/control bus means, in response to signals on the first and second address/control bus means, for supplying an address and address control signals to the first memory means, thereby controlling the first memory means to transfer data via the first data bus means when the processing means accesses the first memory means, for supplying an address and address control signals to the first memory means, thereby controlling the first memory means and gate means to transfer data via the first bus means, the gate means, and the second bus means, and for connecting said first bus means to said second bus means through said gate means when the input/output means accesses the first memory means, and for synchronizing the address and control signals on the first address/control bus means with a bus cycle of the second address control means, transmitting the synchronized address and control signals to the second address/control bus means, and connecting the first data bus means to the second data bus means through said gate means when the processing means accesses the second memory means.

9. A single processor data processing system compatible with a single-CPU system-bus system, comprising:

a first bus including a first address/control bus and a first data bus;

a second bus including a second address/control bus and a second data bus;

a first memory coupled to the first data bus;

a second memory coupled to the second data bus;

a device coupled to the second bus;

a central processing unit (CPU) coupled to the first bus;

gate means for coupling the first data bus to the second data bus when the CPU accesses the second memory or the device accesses the first memory and for decoupling the first data bus from the second data bus when the CPU accesses the first memory or the device accesses the second memory; and

control means, coupled to the first memory, the first address/control bus, and the second address/control bus, for detecting memory to be accessed and a device requesting memory access in response to data on the first and second address/control buses, for controlling the first memory to transfer data via the first data bus when the CPU accesses the first memory, and the second bus when the device accesses the first memory, and for synchronizing data on the first address/control bus with a bus cycle of the second bus and transmitting the synchronized data to the second address/control bus.

10. A single-CPU data processing system compatible with a single-CPU system-bus system, comprising:

first bus means for transmitting data including first address/control bus means for transmitting address and control signals, and first data bus means for transmitting data;

second bus means for transmitting data including second address/control bus means for transmitting address and control signals, and second data bus means for transmitting data;

firsts memory means, coupled to the first data bus means, for storing data;

second memory means, coupled to the second bus means, for storing data;

first access means, coupled to the first bus means, for accessing the first and second memory means;

second access means, coupled to the second bus means, for accessing the first and second memory means;

gate means for coupling the first data bus means to the second data bus means when the first access means accesses the second memory means or the second access means accesses the first memory means and for decoupling the first data bus means from the second data bus means when the first access means accesses the first memory means or the second access means accesses the second memory means; and

control means, coupled to the first memory means, the first address/control bus means, and the second address/control bus means, for controlling the first memory means to transfer data via the first data bus means when the first access means accesses the first memory means, for controlling the first memory means to transfer data via the first bus means, the gate means, and the second bus means when the second access means accesses the first memory means, and for synchronizing the data on the first address/control bus with a bus clock of the second bus and transmitting the synchronized data to the second address/control bus means, when the first access means accesses the second memory means.