Plug-based floating gate memory

• US 5,281,548 A
• Filed: 07/28/1992
• Issued: 01/25/1994
• Est. Priority Date: 07/28/1992
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Prall, Kirk D.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US07/920,793
• Time in Patent Office: 546 Days
• Field of Search: 437/43, 437/48, 437/52
• US Class Current: 438/259
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel

Abstract

A device and a method of forming a floating gate memory transistor of very small area, thereby allowing a high-density integrated circuit chip, more specifically for Erasable Programmable Read-Only Memory (EPROM) or similar non-volatile devices.

In a first embodiment, a method is disclosed that fabricates a programmable memory cell described as a "diffusion cut" cell where a plug-type floating gate contact hole cuts through a diffusion region and partially into a substrate region. In a second embodiment, a method is disclosed that fabricates a programmable memory cell described as an "oxide cut" cell, where the plug-type floating gate contact hole only penetrates a silicon oxide layer. This "oxide cut" cell is formed in a similar fashion except penetration does not go into the diffusion region or substrate.

Claims

1. A method of fabricating a minimum area floating gate memory cell within an IC chip contact well comprising the steps of:

a. growing and patterning a field oxide on a substrate by a LOCOS process;

b. implanting an impurity element in the substrate to form a diffusion region adjacent the field oxide;

c. depositing an oxide layer over the diffusion region and field oxide;

d. patterning and etching a contact well in the oxide layer, field oxide, diffusion region, and substrate further comprising;

i. performing a cell plug masking;

ii. etching the oxide layer;

iii. etching the silicon and diffusion region, thereby forming an extended channel;

e. growing a gate/tunnel oxide layer within the contact well;

f. depositing and doping a first polysilicon layer with the contact well, thereby forming a floating gate and capacitor C1;

g. etching the first polysilicon layer until the only polysilicon is within the contact well forming a polysilicon plug;

h. depositing a second polysilicon layer within the contact well;

i. etching back the second polysilicon layer leaving a thin layer of the second polysilicon on a perimeter of the contact well;

j. depositing an ONO dielectric layer over the second polysilicon layer wherein the ONO dielectric layer is about 100 Å

thick;

k. depositing and doping a third polysilicon layer over the contact hole, thereby forming a second capacitor C2 between the third polysilicon layer and the second polysilicon layer wherein a capacitance ratio of C2/C1 is maximized by controlling a depth of the oxide layer of step c, thereby providing a maximum voltage and charge on the floating gate during electrical programming;

l. depositing a tungsten silicide layer over the third polysilicon layer; and

then

m. masking and etching the third polysilicon layer and tungsten silicide to form a word line.

2. A method of fabricating a minimum area floating gate memory cell within an IC chip contact well comprising the steps of:

a. growing and patterning a field oxide on a substrate by a LOCOS process;

b. implanting an impurity element in the substrate to form a diffusion region adjacent the field oxide;

c. depositing an oxide layer over the diffusion region and field oxide;

d. patterning and etching a contact well in the oxide layer further comprising;

i. performing a cell plug masking;

ii. etching the oxide layer;

iii. etching the silicon and diffusion region, thereby forming an extended channel;

e. growing a gate/tunnel oxide layer within the contact well, thereby forming a floating gate and a capacitor C1 between the first polysilicon layer and the substrate, said capacitor C1 having a minimal capacitance;

f. depositing and doping a first polysilicon layer within the contact well, thereby forming a floating gate and capacitor C1;

g. etching the first polysilicon layer until the only polysilicon is within the contact well forming a polysilicon plug;

h. depositing a second polysilicon layer within the contact well;

i. etching back the second polysilicon layer leaving a thin layer of the second polysilicon on a perimeter of the contact well;

j. depositing an ONO dielectric layer over the second polysilicon layer wherein the ONO dielectric layer is about 100 Å

thick;

k. depositing and doping a third polysilicon layer over the contact hole, thereby forming a second capacitor C2 between the third polysilicon layer and the second polysilicon layer C2 having a larger capacitance than C1;

l. depositing a tungsten silicide layer over the third polysilicon layer; and

then

m. masking and etching the third polysilicon layer and tungsten silicide to form a control gate and word line.