Power semiconductor device having gate structure in trench

• US 5,282,018 A
• Filed: 04/29/1993
• Issued: 01/25/1994
• Est. Priority Date: 01/09/1991
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Baba, Yoshiro, Hiraki, Shunichi
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Meier, Stephen D.
• Application Number:
  US08/053,811
• Time in Patent Office: 271 Days
• Field of Search: 357/23.4, 257/296, 257/297, 257/305
• US Class Current: 257/296
• CPC Class Codes: H01L 21/74 Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOS semiconductor device, such as a vertical MOSFET, IGBT, and IPD, includes a body of semiconductor material having a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type and formed in the first semiconductor layer to provide a channel, a third semiconductor layer having the first conductivity type and formed in the second semiconductor layer, a trench formed in the first semiconductor layer across the third and second semiconductor layers, a gate insulating film covering a surface of the trench and extending to a surface of the third semiconductor layer, a gate electrode layer provided on the gate insulating film, and a buried layer having the first conductivity type provided in the first semiconductor layer so as to be contiguous to a bottom of the trench.

Claims

1. A power MOS semiconductor device, comprising:

a body of semiconductor material including a first semiconductor layer of a first conductivity type and a substrate having an impurity concentration, said first semiconductor layer having an impurity concentration lower than said impurity concentration of said substrate;

a second semiconductive layer of a second conductivity type having a high impurity concentration and disposed in said first semiconductor layer to provide a channel;

a third semiconductive layer of said first conductivity type having a high impurity concentration and disposed in said second semiconductor layer;

a trench disposed in said first semiconductor layer across said second and third semiconductor layers, said trench having a bottom and a depth deep enough to reduce an electric field concentration at said bottom of said trench;

a buried layer of said first conductivity type disclosed in said first semiconductor layer, said buried layer contacting said substrate and being located between said bottom and said trench and said substrate, said buried layer having an impurity concentration approximately in the range of 5×

10¹⁵ cm^-3 to 1×

10¹⁷ cm^-3 ;

a gate insulating film covering a surface of said trench and extending to a surface of said third semiconductor layer; and

a gate electrode layer provided on said gate insulating film.

2. The power MOS semiconductor device according to claim 1, wherein said bottom of said trench is located close enough to said substrate to minimize an on-resistance of the semiconductor device.

3. The power MOS semiconductor device according to claim 1, wherein said substrate has a high impurity concentration of said first conductivity type and provides a vertical power MOSFET.

4. The power MOS semiconductor device according to claim 1, wherein said substrate has a high impurity concentration of said second conductivity type and the power MOS semiconductor device further comprises a fourth semiconductor layer having a high impurity concentration of said first conductivity type to provide an insulated gate bipolar transistor.

5. The power MOS semiconductor device according to claim 4, wherein said buried layer is provided between said bottom of said trench and said fourth semiconductor layer, said buried layer contacting said fourth semiconductor layer.

6. The power MOS semiconductor device according to claim 1, wherein said substrate has a high impurity concentration of said second conductivity type to provide an insulated gate bipolar transistor.

7. The power MOS semiconductor device according to claim 1, wherein said depth of said trench controls an on-resistance of said semiconductor device.

8. The power MOS semiconductor device according to claim 1, wherein said buried layer reduces an electric field at said bottom of said trench.

9. The power MOS semiconductor device according to claim 1, wherein said substrate of said first conductivity type provides a plurality of small signal circuit regions isolated from one another.

10. The power MOS semiconductor device according to claim 9, wherein each of said plurality of small signal circuit regions includes a MOSFET.

11. The power MOS semiconductor device according to claim 9, wherein each of said plurality of small signal circuit regions includes a bipolar transistor.