Transistor antifuse for a programmable ROM

• US 5,282,158 A
• Filed: 08/21/1992
• Issued: 01/25/1994
• Est. Priority Date: 08/21/1992
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Roger R.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Niranjan, Frank
• Application Number:
  US07/934,024
• Time in Patent Office: 522 Days
• Field of Search: 257/529, 257/530, 257/532, 257/288, 257/301, 257/377, 365/96, 365/102, 365/103, 365/105, 365/149, 365/225.7
• US Class Current: 365/96
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

A programmable read-only memory device and method of fabrication are disclosed having an antifuse in the drain node of a field effect transistor. Programming is accomplished by imposing a high voltage on the transistor drain and gate which causes the antifuse to be a closed circuit; otherwise, the transistor appears as an open circuit. Locating the antifuse in the drain node as opposed to the source node avoids problems of source reverse bias.

Claims

1. A programmable read-only memory (PROM) chip having pairs of MOSFET devices comprising:

(a) a gate oxide formed over substrate;

(b) a pair of gates formed over the gate oxide;

(c) a drain diffusion formed between the gates;

(d) a pair of source diffusions formed on an outside area of the gates;

(e) a source line formed over the pair of source diffusions;

(f) a trench formed between the pair of gates separating the drain diffusion into a first and second drain diffusion;

(g) an insulating oxide grown within the trench;

(h) an antifuse material deposited over the pair of MOSFET devices and having electrical contact with the first and second diffusions; and

(i) a bit line deposited over the trench and drain diffusions, wherein applying a voltage on the bit line and source line shorts the antifuse material thereby creating a functional MOSFET, and not applying a voltage on the bit line and source line provides an open circuit.

2. The PROM chip of claim 1 wherein the gates further comprise:

(a) a doped polysilicon layer over the gate oxide;

(b) a tungsten silicide layer over the doped polysilicon layer; and

(c) an oxide layer over the tungsten silicide layer.

3. The PROM chip of claim 2 wherein the antifuse material is selected from the group consisting of silicon oxide and silicon nitride.