Interrupt distribution scheme for a computer bus

• US 5,282,272 A
• Filed: 01/28/1993
• Issued: 01/25/1994
• Est. Priority Date: 12/21/1990
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Trethewey, Jim R., McArdle, Brian J., Bhasker, Narjala, Gutmann, Michael J., Cadambi, Sudarshan B., Guy, Charles B.
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): HAFIZ, TARIQ R
• Application Number:
  US08/010,486
• Time in Patent Office: 362 Days
• Field of Search: 395/275, 395/325, 395/725
• US Class Current: 710/116
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A method of handling processor to processor interrupt requests in a multiprocessing computer bus environment is described. This method allows a multiple-tiered, increasing priority, interrupt request scheme. This method also allows processor to processor directed interrupt requests, processor to one processor of a group of processors interrupt requests, and processor to all processors of a group of processors interrupt requests.

Claims

1. A method for having a first processor request a second processor of a computer system to perform an interrupt operation, wherein the computer system includes a plurality of processors including the first processor and the second processor, wherein the plurality of processors are coupled to a bus, wherein each of the plurality of processors has a processing priority based on a predetermined priority of a program being executed on the respective one of the plurality of processors, comprising the steps of:

(a) generating in the first processor an interrupt request with an interrupt priority for the second processor;

(b) sending the interrupt request to the second processor via the bus, wherein the second processor performs the interrupt operation if the interrupt request has an interrupt priority higher than the processing priority of the second processor, wherein if the second processor accepts the interrupt request, the second processor returns an acknowledgement to the first processor via the bus, wherein the second processor does not accept the interrupt request and does not return the acknowledgement to the first processor if the interrupt priority of the interrupt request is not higher than the processing priority of the second processor;

(c) determining if the acknowledgement is received in the first processor;

(d) if the acknowledgement is not received, then

(1) resending the interrupt request from the first processor to the second processor with the interrupt priority;

(2) determining if the acknowledgement is received in the first processor;

(3) if the acknowledgement is still not received, then repeating steps (d)(1) through (d)(2) if the steps (d)(1) through (d)(2) have been repeated fewer than X times, wherein X is a nonzero positive integer;

(e) if the acknowledgement is still not received and if the steps (d)(1) through (d)(2) have been repeated the X times, then

(1) increasing the interrupt priority of the interrupt request to an adjacent higher level in the first processor if the interrupt priority has not reached a highest level;

(2) resending the interrupt request with the increased interrupt priority from the first processor to the second processor;

(3) determining if the acknowledgement is received in the first processor;

(4) if the acknowledgement is still not received, then repeating steps (e)(2) through (e)(3) if the steps (e)(2) through (e)(3) have been repeated fewer than Y times, wherein Y is a nonzero positive integer;

(f) if the acknowledgement is still not received and if the steps (e)(2) through (e)(3) have been repeated the Y times, then repeating steps (e)(1) through (e)(4) until it has been determined that the first processor has received the acknowledgement; and

(g) if the acknowledgement is received in the first processor, then stopping resending the interrupt request to the second processor.

2. The method of claim 1, further comprising the step of increasing the interrupt priority of the interrupt request in the first processor at any time.

3. The method of claim 1, wherein the step (e)(1) increases the interrupt priority to a highest user program priority.

4. The method of claim 1, wherein the step (e)(1) increases the interrupt priority to a highest processing priority of the computer system.

5. The method of claim 1, wherein the plurality of processors consist only of the first and second processors.

6. The method of claim 1, wherein the plurality of processors include processors in addition to the first and second processors.

7. The method of claim 6, wherein the step (b) further comprises the step of broadcasting the interrupt request to a group of the plurality of processors, wherein each of the group of the plurality of processors can be the second processor to accept the interrupt request when its respective processing priority is lower than the interrupt priority of the interrupt request.

8. The method of claim 6, wherein the step (b) further comprises the step of broadcasting the interrupt request to a group of the plurality of processors, wherein the interrupt request is destined for each of the group of the plurality of processors.

9. The method of claim 6, wherein the step (b) further comprises the step of broadcasting the interrupt request to each of the plurality of processors, excluding the first processor, wherein the interrupt request is destined for each of the plurality of processors, excluding the first processor.

10. The method of claim 6, further comprising the step of resending the interrupt request to a third processor at any time.

11. The method of claim 1, further comprising the step of stopping resending the interrupt request at any time.

12. The method of claim 1, further comprising the step of polling a status register in the first processor to monitor current status of the interrupt request.

13. The method of claim 1, wherein the X has a value of four, where the Y has a value of four.