Multi-layer circuit construction methods with customization features

• US 5,282,312 A
• Filed: 12/31/1991
• Issued: 02/01/1994
• Est. Priority Date: 12/31/1991
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Grube, Gary W., Khandros, Igor Y., DiStefano, Thomas H.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US07/816,634
• Time in Patent Office: 763 Days
• Field of Search: 29/830, 29/846, 29/852, 156/902, 427/96, 427/97, 228/179
• US Class Current: 29/830
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01R 12/523 by an interconnection through aligned holes in the boards or multilayer board
• CPC Class Codes: H05K 1/0287 having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
• CPC Class Codes: H05K 1/029 having a programmable lay-out, i.e. adapted for choosing between a few possibilities
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 2201/0195 Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
• CPC Class Codes: H05K 2201/0305 Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/09609 Via grid, i.e. two-dimensional array of vias or holes in a single plane interposers H05K2201/10378
• CPC Class Codes: H05K 2201/09945 Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
• CPC Class Codes: H05K 2201/10378 Interposers
• CPC Class Codes: H05K 2201/10666 Plated through-hole for surface mounting on PCB
• CPC Class Codes: H05K 2203/175 Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
• CPC Class Codes: H05K 3/4038 : Through-connections; Vertical interconnect access [VIA] connections H05K3/403, H05K3/42 take precedence
• CPC Class Codes: H05K 3/4069 : for via connections in organic insulating substrates
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/462 : characterized by laminating only or mainly similar double-sided circuit boards
• CPC Class Codes: H05K 3/4623 : the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottomend of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.

Claims

1. A method of making a multilayer circuit assembly comprising the steps of:

(a) providing a first circuit panel having a dielectric body with oppositely directed top and bottom surfaces, contacts on its top surface at locations of a first pattern terminals on its bottom surface, and through-conductors electrically connected to said terminals and extending to the top surface of the panel, and a second circuit panel having a dielectric body with a bottom surface and terminals at locations of said first pattern on the bottom surface of such panel, saidproviding step including the step of customizing said first circuit panel by selectively treating the top surface of such panel so that less than all of the through conductors of such panel are connected to contacts of such panel;

(b) stacking said circuit panels in superposed, top-surface to bottom surface relation so that the top surface of said first circuit panel faces the bottom surface of said second circuit panel at a first interface and said first patterns on said facing surfaces are in registration with one another, with said contacts of said first panel being aligned with said terminals of said second panel at at least some locations of said in-registration patterns; and

(c) nonselectively connecting all of said aligned contacts and terminals at said interface, whereby less than all of said through conductors of said customized panel are connected to terminals of said adjacent panel.

2. A method as claimed in claim 1 wherein said dielectric body of said second circuit panel has a top surface directed oppositely from its bottom surface, and through conductors electrically connected to at least some of the terminals on the bottom surface of such panel extending to the top surface of the panel, whereby less than all of the through conductors of said first panel will be connected to through conductors of said second panel to form composite vertical conductors extending through both said first and second panels.

3. A method as claimed in claim 2 wherein said second panel has terminals at all locations of said first pattern and through conductors connected to all of said terminals, whereby all of those through conductors of said first panel which are connected to contacts of such panel will be connected with through conductors of the second panel to form composite vertical conductors.

4. A method as claimed in claim 2 wherein said step of nonselectively connecting includes the steps of placing an interposer bearing discrete masses of flowable conductive material at said interface so that said masses are disposed at all locations of said first pattern at said first interface and bringing all of the flowable conductive material of said interposer to a fluid condition.

5. A method as claimed in claim 4 further comprising the step of bonding said dielectric bodies of said first and second panels to one another.

6. A method as claimed in claim 5 wherein said bonding step includes the step of bringing flowable dielectric material on said interposer to a flowable condition concomitantly with said step of bringing said flowable conductive material to a fluid condition.

7. A method as claimed in claim 2 wherein said providing step further includes the step of selectively treating the top surface of said second panel, said selective treatment steps being performed so as to selectively connect through conductors of each of said first and second panels to surface conductors extending along the top surface of each said panel.

8. A method as claimed in claim 7 wherein said providing step further includes the step of selectively treating the bottom surfaces of said panels so as to selectively connect through conductors of each said panel to surface conductors extending along the bottom surface of each said panel.

9. A method as claimed in claim 8 wherein said steps of selectively treating the top surfaces of said panel include the step of selectively connecting said contacts with surface conductors on said top surfaces.

10. A method as claimed in claim 8 wherein said surface conductors are formed in said selective treatment steps.

11. A method as claimed in claim 10 wherein said providing step includes the step of providing said panels as circuit panel precursors having said through-conductors formed therein and having a layer of electrically conductive material on each of said top and bottom surfaces, and wherein said selective treatment steps include the steps of providing resist patterns on said layers and exposing said layer to one or more treatment media so that after such exposure electrically conductive material remains only at areas of said layers not covered by said resist pattern.

12. A method as claimed in claim 11 wherein said step of providing said resist pattern on at least some of said conductive layers includes the step of forming said resist pattern by photographically exposing a layer of resist to patternwise illumination so as to define resist areas corresponding to said surface conductors and simultaneously define resist areas corresponding to fiducial marks, whereby fiducial marks will be formed on at least some of said surfaces of said panels in predetermined spatial relation with said surface conductors thereon, said stacking step including the step of aligning said panels with reference to said fiducial marks.

13. A method as claimed in claim 12 wherein said step of nonselectively connecting includes the step of placing an interposer bearing discrete masses of conductive material at all locations of said first pattern at said first interface, said interposer having fiducial marks thereon in preselected spatial relation to said discrete masses, said step of placing said interposer including the step of aligning said interposer according to said fiducial marks thereon.

14. A method as claimed in claim 13 wherein at least one of said interposer and said circuit panels has fiducial marks in the form of groups of holes arranged at preselected spacings, said fiducial marks on another one of said interposer and said circuit panels including groups of spots arranged at preselected spacings different from the preselected spacings of said holes so that a spot of each group can be aligned with only one hole of that group, said step of placing said interposer including the step of determining alignment of said interposer relative to one of said panels by determining which of said holes in each group is aligned with a spot.

15. A method as claimed in claim 12 wherein said step of photographically exposing includes the step of simultaneously exposing said layers of resist on both the top and bottom surfaces of at least one said panel to said illumination so as to form fiducial marks on both said top and bottom surfaces of such panel.

16. A method as claimed in claim 8 wherein said surface conductors on the top and bottom surfaces of each said circuit panel extend in mutually perpendicular first and second directions on such panel, and wherein said stacking step is performed so that the first directions of said panels are aligned with one another and the second directions of said panels are aligned with one another.

17. A method as claimed in claim 16 wherein each said through conductor of said first and second panels extends substantially vertically between the top and bottom surfaces of each panel and each said terminal is disposed substantially at the bottom end of a through conductor, the contacts of said first panel being offset from the terminals and through conductors of such panel in said first direction, said stacking step including the step of arranging said panels so that the through conductors of said second panel are offset from the through conductors of said first panel in said first direction.

18. A method as claimed in claim 17 wherein said first panel has a generally sheetlike internal electrically conductive element disposed between said top and bottom surfaces and risers extending from said internal element to said bottom surface at riser locations spaced apart from the through conductors in said second direction, said step of selectively treating said bottom surfaces including the step of selectively connecting through conductors and surface conductors of said panels to the risers thereof.

19. A method as claimed in claim 7 wherein said step of selectively treating said top surface of said second circuit panel is performed so as to connect less than all of said through conductors of said second circuit panel to contacts disposed on the top surface of said second circuit panel at locations of a second pattern, the method further including the steps of providing a third circuit panel having a dielectric body defining top and bottom surfaces, said third panel having terminals on its bottom surface at locations of said second pattern, superposing said third panel on said second panel so that the bottom surface of said third panel faces the top surface of said second panel at a second interface, and so that said second patterns are in registration with one another, whereby contacts of said second panel and terminals of said third panel are aligned with one another at said second interface, and nonselectively connecting all of said aligned terminals and contacts at said second interface.

20. A method as claimed in claim 19 wherein said third panel has a top surface and through conductors extending from the terminals of such panel to the top surface thereof, the through conductors of each of said first, second and third panels extending substantially vertically between the to and bottom surfaces of such panel, the stacking and superposing steps being performed so that the through conductors of the first and third panels are aligned with one another.