High density power device fabrication process

• US 5,283,201 A
• Filed: 08/07/1992
• Issued: 02/01/1994
• Est. Priority Date: 05/17/1988
• Status: Expired due to Term

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Advanced Power Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Meyer, Theodore O., Pike, Douglas A. Jr., Mosier, John W. II, Tsang, Dah W.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): EVERHART, BYRON S
• Application Number:
  US07/927,169
• Time in Patent Office: 543 Days
• Field of Search: 437/6, 437/31, 437/40, 437/41, 437/50, 257/213, 257/288, 257/327, 257/341, 257/343
• US Class Current: 438/138
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28'"'"') between spacer inner surfaces (48). This area is doped to form a source layer (72) atop the body layer (26'"'"') and then trenched to form a second trench (80) having sidewalls aligned to the spacer inner surfaces. Second trench (80) defines vertically-oriented source and body layers (86, 90) stacked along gate oxide layer (60) to form vertical channels on opposite sides of second trench (80).

Claims

1. A method of making a recessed gate field effect power MOS device, the method comprising:

forming a substrate (20) including first and second doped layers (24,

     26) of first and second opposite dopant polarities to define a body region adjoining an upper surface of the substrate and an underlying drain region;

forming a trenching protective layer (30) on the upper surface (28) of the substrate;

masking and patterning the trenching protective layer to define an exposed first area (46) and a protected second area of the upper surface of the substrate demarcated by opposite sidewalls of the trenching protective layer;

forming sidewall spacers (44) having inner surfaces (48) contacting opposite sidewalls of the trenching protective layer (30) and outer surfaces (47) spaced a predetermined spacing (54) from the sidewalls of the trenching protective layer;

forming in the first area (46) of the substrate, between the outer surfaces (47) of the sidewall spacers (44) , a first trench (50) having sidewalls aligned relative to the outer surfaces (47) of the sidewall spacers and extending at least through the layer (26) defining the body region to a bottom wall at least a predetermined depth (56) from the upper surface of the substrate;

forming a gate oxide layer (60) on the first trench sidewalls;

filling the first trench with polysilicon (62) to a level (64) spaced between the upper surface of the substrate and a top surface of the trenching protective layer (30);

applying a protective layer (68) selectively over the polysilicon (62) filled into the first trench, between the sidewall spacers (44) and in contact with the outer surfaces (47) of the sidewall spacers;

removing the trenching protective layer to expose the second area of the upper surface (28'"'"') of the substrate between the inner surfaces (48) of the sidewall spacers;

doping the second area of the upper surface (28'"'"') of the substrate between the gate oxide layer (60) on the trench sidewalls with dopant of said second dopant polarity to form a source region (72) atop the body region (26'"'"');

forming, in the second area of the substrate (28'"'"') between the inner surfaces (48) of the sidewall spacers (44), a second trench (80) having sidewalls aligned relative to the inner surfaces of the sidewall spacers and extending through the layer (72) defining the source region to a bottom wall in the body region (26") of the substrate; and

depositing a source conductive layer (94) in the second trench in contact with the source region and the body region;

the second trench (80) through the source region and body region defining vertically-oriented source and body layers (86,

     90) stacked along the gate oxide layer (60) on opposite sidewalls of the second trench (80) and having a lateral thickness (88) established by the predetermined spacing of the inner and outer surfaces of the sidewall spacers.

2. A method according to claim 1 in which the body layer (90) is sized to a lateral thickness (88) less than a vertical height (83) thereof.

3. A method according to claim 1 in which the body layer (90) is sized to a lateral thickness (88) less than 1 μ

m.

4. A method according to claim 3 in which the vertically-oriented body layer (90) is doped to a first doping concentration and a laterally-extending portion of the body region (26") is doped to a second doping concentration greater than the first doping concentration.

5. A method according to claim 1 including forming an insulative layer (68) between the sidewall spacers (44) over the source conductor (94) to electrically isolate the gate conductor (62) from the source conductor.

6. A method according to claim 1 in which the second trench is formed to a depth (82) such that the source conductive layer (94) extends vertically along both the source and body layers (86, 90) to form a short across a PN junction formed therebetween and contacts a laterally-extending upper surface of the body region (26) at a position spaced below the PN junction.

7. A method according to claim 1 in which substrate (20) includes a base layer (122) underlying the first doped layer (24) and doped with a dopant of said first polarity to a doping concentration greater than a doping concentration of the first doped layer (24) to form a three-layer power MOSFET.

8. A method according to claim 7 in which the first trench is formed to a depth (156) extending into the base layer and the gate oxide layer is formed in a first portion (160A) having first thickness in a lower portion of the trench and a second portion (160B) having a second thickness in an upper portion of the trench, the first thickness being greater than the second thickness.

9. A method according to claim 1 in which substrate (20) includes a base layer (22) underlying the first doped layer (24) and doped with a dopant of said second polarity to define a four-layer PNPN device.

10. A method according to claim 9 in which the first trench is formed to a depth (256) within the first layer spaced above the base layer and the gate oxide layer is formed in a first portion (260A) having a first thickness in a lower portion of the trench and a second portion (260B) having a second thickness in an upper portion of the trench, the first thickness being greater than the second thickness.

11. A method according to claim 1 in which:

the first trench is formed to a first depth;

a first gate oxide layer (160A, 260A) is formed with a first thickness;

a filler material is filled into the trench to a second depth less than the first depth;

a portion of the first gate oxide layer is removed above the filler material;

a second gate oxide layer (160B, 260B) is formed with a second thickness; and

the trench is filled above said second depth with a conductive gate material.

12. A method according to claim 11 in which the filler material includes polysilicon and the second gate oxide layer (160B, 260B) is formed over the polysilicon.

13. A method according to claim 11 in which the filler material includes photoresist and the photoresist is removed before the second gate oxide layer is formed.

14. A method according to claim 1 in which the trenching protective layer comprises a thin oxide layer (32) formed atop the upper substrate surface, a polysilicon layer deposited on the thin oxide layer, and a thick oxide layer (36) deposited on the polysilicon layer.

15. A method according to claim 1 in which the trenching protective layer (330) comprises a first oxide layer (32) formed atop the upper substrate surface, a first polysilicon layer (34, 334) deposited on the first oxide layer, a second oxide layer (36, 336) formed on the first polysilicon layer;

and a second polysilicon layer (338) deposited on the second oxide layer.

16. A method according to claim 1 in which the first trench and the gate oxide layer and gate conductor within the first trench define a gate structure which is laterally patterned in two dimensions to define an interconnected matrix enclosing a plurality of islands, each island being formed with said second trench extending into a central portion thereof and containing a downward extending finger of source conductor surrounded by a portion of the source and body layers (86, 90) including a vertical channel having a width defined in each island by a perimeter of the island.

17. A method according to claim 16 in which the body layer (90) is sized to a lateral thickness (88) proportionate to the predetermined spacing (52) between the inner surfaces (48) and outer surfaces (47) of the sidewall spacers (44).

18. A method according to claim 1 including forming at least two of said first trenches at a predetermined lateral spacing and forming said second trench between the first trenches at a spacing therefrom determined by said predetermined spacing (52) between the inner and outer surfaces of the sidewall spacers, the first trenches each containing the gate oxide layer and gate conductor, the source conductor extending into the second trench and contacting the vertically oriented source and body layers (86,90) on opposite sides thereof.

19. A method according to claim 18 in which the body layer (90) is sized to a lateral thickness (88) proportionate to the predetermined spacing (52) between the inner surfaces (48) and outer surfaces (47) of the sidewall spacers (44).

20. A method according to claim 1 in which the body layer (90) is sized to a lateral thickness (88) proportionate to the predetermined spacing (52) between the inner surfaces (48) and outer surfaces (47) of the sidewall spacers (44).