IGBT device with platinum lifetime control having gradient or profile tailored platinum diffusion regions

• US 5,283,202 A
• Filed: 09/15/1992
• Issued: 02/01/1994
• Est. Priority Date: 03/21/1986
• Status: Expired due to Term

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Advanced Power Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Scrulla, Dumitra, Pike, Douglas A. Jr., Katana, James M., Tsang, Dah W.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): EVERHART, BYRON S
• Application Number:
  US07/945,817
• Time in Patent Office: 504 Days
• Field of Search: 437/29, 437/31, 437/40, 437/41, 437/247, 257/213, 257/288, 257/365, 257/368, 257/378
• US Class Current: 438/543
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/221 of killers
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 438/904 Charge carrier lifetime control
• CPC Class Codes: Y10S 438/917 Deep level dopants, e.g. gold, chromium, iron or nickel

Abstract

For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (˜10¹⁴ /cm³) to block reverse bias voltage. The N+ layer is >20 μm thick and doped below ˜10¹⁷ /cm³ but above the N- doping to enhance output impedance and reduce gain at high V_ce conditions. Or the N+ layer is formed with a thin (˜5 μm) highly doped (>10¹⁷ /cm³) layer and a thick (>20 μm) layer of ˜10¹⁶ /cm³ doping. A platinum dose of 10¹³ to 10¹⁶ /cm² is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non-polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si--H into the film.

Claims

1. In a fabrication process for making a semiconductor power device having at least one PN junction, an improved minority carrier lifetime control process comprising:

selecting a transition metal having a deep level in silicon suitable for recombination;

determining a maximum dose of the selected transition metal that can be fully dissolved into the substrate at a temperature in a range between a eutectic temperature of the substrate and an annealing temperature of the substrate;

determining and depositing a dose of the transition metal not exceeding the maximum dose sufficient to effect lifetime control without substantially increasing leakage current of the device; and

diffusing the metal atoms throughout the substrate at a temperature within said range, including;

diffusing a first portion of the dose throughout the substrate; and

diffusing a second portion of the dose in a gradient band near a selected surface of the substrate.

2. In a fabrication process for making a semiconductor power device on a substrate having at least one PN junction, an improved minority carrier lifetime control process comprising:

selecting a transition metal having a deep level in silicon suitable for recombination;

determining a maximum dose of the selected transition metal that can be fully dissolved into the substrate at a temperature in a range between a eutectic temperature of the substrate and an annealing temperature of the substrate;

determining and depositing on a surface of the substrate adjacent the PN junction, a dose of the transition metal not exceeding the maximum dose sufficient to effect lifetime control without substantially increasing leakage current of the device; and

diffusing the metal atoms throughout the substrate at a temperature within said range, including profile tailoring the concentration of transition metal atoms in the substrate relative to the surface of the substrate.

3. The fabrication process of claim 2 wherein the selected transition metal is diffused through the substrate using a rapid thermal anneal process.

4. The fabrication process of claim 3 wherein the amount of time required to perform the rapid thermal anneal process ranges from five seconds to 20 seconds.

5. The fabrication process of claim 3 wherein the amount of time required to perform the rapid thermal anneal process is less than one minute.

6. The fabrication process of claim 2 wherein the elected transition metal is either platinum or gold.

7. The fabrication process of claim 2 wherein the transition metal is tailored to have a relatively shallow profile compared to a completed diffusion throughout the entire substrate.

8. The fabrication process of claim 2 wherein the dose of selected transition metal is in the range of 1×

10¹¹ to 1×

10¹⁶ atoms/cm².