Method of forming passivation oxidation for improving cell leakage and cell area

• US 5,283,204 A
• Filed: 04/15/1992
• Issued: 02/01/1994
• Est. Priority Date: 04/15/1992
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Semiconductor, Inc. (Micron Technology, Inc.)
• Inventors: Rhodes, Howard E., Lowrey, Tyler A.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US07/869,571
• Time in Patent Office: 657 Days
• Field of Search: 437/52, 437/919, 148/DIG. 109, 257/306, 257/307, 257/532
• US Class Current: 438/253
• CPC Class Codes: H01L 28/86 having horizontal extensions
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

The invention is directed to maximizing storage cell surface area in a high density/high volume DRAM (dynamic random access memory) fabrication process. Fabrication methods are disclosed that, when used with existing capacitor fabrication processes, will reduce cell leakage and allow for increased capacitance. The present invention corrects any severed storage node poly that may have resulted from a misalignment of a masking pattern used for defining future buried contacts by placing passivation oxidation over the existing wafer surface which, in effect, seals off the severed storage node poly form the capacitor'"'"'s top cell plate poly. The passivation oxidation prevents cell plate to plate leakage while protecting the severed storage node poly from subsequent deposition of conductive layers.

Claims

1. A process for isolating first and second conductive plates of a storage capacitor fabricated on a starting substrate, said process comprising the steps of:

a) providing a mask having an opening aligned over a desired buried contact location between neighboring capacitor storage node plates and a pair of parallel conductive access lines thereby exposing a portion of said capacitor'"'"'s second conductive plate;

b) removing said second conductive plate'"'"'s exposed portion and an underlying portion of a cell dielectric layer thereby exposing an underlying insulating layer, said removal of second conductive plate'"'"'s exposed portion and said underlying portion of said cell dielectric layer thereby exposes and severs a portion of said first conductive plate resulting from a misalignment of said mask opening;

c) removing said insulative layer thereby exposing a portion of the starting substrate and forming insulative spacers on walls of said pair of parallel conductive access lines;

d) removing said mask;

e) introducing conductive impurities into said exposed starting substrate;

f) oxidizing the resulting surface prior to an annealing step, said annealing step drives said conductive impurities deeper into said exposed starting substrate, said oxidation insulates said severed portions of said first conductive plate.

2. A process as recited in claim 1, wherein said oxidizing step is a wet oxidation step.

3. A process as recited in claim 1, wherein said oxidizing step is a dry oxidation step.

4. A process as recited in claim 1, wherein said annealing step is performed at a temperature range of approximately 700°

-900°

C.

5. A process as recited in claim 1, wherein said annealing step is performed at a temperature of approximately 800°

C.

6. A process as recited in claim 1, wherein said first and second conductive plates are doped polysilicon.

7. A process as recited in claim 1, wherein the storage capacitor comprises a stacked capacitor.

8. A process as recited in claim 1, wherein said starting substrate is a silicon substrate.

9. A process as recited in claim 1, wherein the mask comprises a photoresist layer.

10. A process as recited in claim 1, wherein said parallel conductive access lines are wordlines in dynamic random access memory.

11. A process for isolating first and second conductive plates of a DRAM storage capacitor fabricated on a silicon substrate, said process comprising the steps of:

a) providing a mask having an opening aligned over a desired buried contact location between neighboring capacitor storage node plates and a pair of parallel conductive access lines thereby exposing a portion of said capacitor'"'"'s second conductive plate;

b) removing said second conductive plate'"'"'s exposed portion and an underlying portion of a cell dielectric layer thereby exposing an underlying insulating layer, said removal of second conductive plate'"'"'s exposed portion and said underlying portion of said cell dielectric layer thereby exposes and severs a portion of said first conductive plate resulting from a misalignment of said mask opening;

c) removing said insulative layer thereby exposing a portion of the silicon substrate and forming insulative spacers on walls of said pair of parallel conductive wordlines;

d) removing said mask;

e) introducing conductive impurities into said exposed starting substrate;

f) oxidizing the resulting surface prior to an annealing step, said annealing step drives said conductive impurities deeper into said exposed silicon substrate, said oxidation insulates said severed portions of said first conductive plate.

12. A process as recited in claim 11, wherein said oxidizing step is a wet oxidation step.

13. A process as recited in claim 11, wherein said oxidizing is a dry oxidation step.

14. A process as recited in claim 11, wherein said annealing step is performed at a temperature range of approximately 700°

-900°

C.

15. A process as recited in claim 11, wherein said annealing step is performed at a temperature of approximately 800°

C.

16. A process as recited in claim 11, wherein said first and second conductive plates are doped polysilicon.

17. A process as recited in claim 11, wherein the storage capacitor comprises a stacked capacitor.

18. A process as recited in claim 11, wherein the mask comprises a photoresist layer.

19. A process for isolating first and second conductive plates of a DRAM storage capacitor fabricated on a silicon substrate, said process comprising the steps of:

a) providing a mask having an opening aligned over a desired buried contact location between neighboring capacitor storage node plates and a pair of parallel conductive access lines thereby exposing a portion of said capacitor'"'"'s second conductive plate;

b) removing said second conductive plate'"'"'s exposed portion and an underlying portion of a cell dielectric layer thereby exposing an underlying insulating layer, said removal of second conductive plate'"'"'s exposed portion and said underlying portion of said cell dielectric layer thereby exposes and severs a portion of said first conductive plate resulting from a misalignment of said mask opening;

c) removing said insulative layer thereby exposing a portion of the silicon substrate and forming insulative spacers on walls of said pair of parallel conductive wordlines;

d) removing said mask;

e) introducing conductive impurities into said exposed starting substrate;

f) oxidizing said surface during an annealing step, said annealing step drives said conductive impurities deeper into said exposed starting substrate.

20. A process as recited in claim 19, wherein said oxidizing step is a wet oxidation step.

21. A process as recited in claim 19, wherein said oxidizing step is a dry oxidation step.

22. A process as recited in claim 19, wherein said annealing step is performed at a temperature range of approximately 700°

-900°

C.

23. A process as recited in claim 19, wherein said annealing step is performed at a temperature of approximately 800°

C.

24. A process as recited in claim 19, wherein said first and second conductive plates are doped polysilicon.

25. A process as recited in claim 19, wherein the storage capacitor comprises a stacked capacitor.

26. A process as recited in claim 19, wherein the mask comprises a photoresist layer.