Distributed cell monolithic mircowave integrated circuit (MMIC) field-effect transistor (FET) amplifier

• US 5,283,452 A
• Filed: 02/14/1992
• Issued: 02/01/1994
• Est. Priority Date: 02/14/1992
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Shih, Yi-Chi, Hwang, Vincent, Le, Huy M., Wang, David C., Chi, Tom Y.
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US07/837,448
• Time in Patent Office: 718 Days
• Field of Search: 357/22 I, 357/22 J, 357/22 K, 357/22 H, 257/275, 257/276, 257/277, 257/280
• US Class Current: 257/277
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence

Abstract

A distributed cell field-effect transistor (FET) amplifier (40) includes a plurality of parallel, elongated source (46a) and drain (46b) regions of individual FET unit cells (46) formed in a substrate (42) in transverse alternating relation, with a plurality of elongated channel regions (46c) being formed between and parallel to adjacent source (46a) and drain (46b) regions respectively. A source foot (48) and a drain foot (50) extend perpendicular to the source (46a) and drain (46b) regions on opposite longitudinally spaced sides thereof respectively. A gate foot (52) extends parallel to the source (48) and drain (50) feet, between the source foot (48) and the cells (46). Source (54) and drain (56) pads and gate (58) fingers extend from the source (48), drain (50) and gate (52) feet into electrical connection with the respective source (46a), drain (46b) and gate ( 46c) regions respectively. The source pads (54) include airbridge portions (54b) which extend over the gate foot (52) without making contact therewith. A fixed tuning circuit (70) is connected between the gate foot (52) and source foot (48), including an inductive stub (72) having a first end connected to the gate foot (52) and a second end, and a capacitor (74) having a first plate (74a) which is integral with the source foot (48) and a second plate connected to the second end of the stub (72). The integration of the capacitor (74) with the source foot (48) enables the amplifier (40) to be tuned at the gate foot (52), thereby eliminating undesirable coupling effects and the need for a separate via for the tuning circuit (70).

Claims

1. A distributed field-effect transistor (FET) amplifier, comprising:

a substrate;

a plurality of parallel, elongated source and drain regions formed in the substrate in transverse alternating relation;

a plurality of elongated channel regions formed in the substrate between and parallel to the adjacent source and drain regions respectively;

an elongated source foot extending substantially perpendicular to the source regions on a first longitudinally spaced side of the source, drain and gate regions;

an elongated drain foot extending substantially perpendicular to the drain regions on a second longitudinally spaced side of the source, drain and gate regions which is opposite to said first side;

an elongated gate foot extending substantially perpendicular to the gate regions on said first side between the source foot and the source, drain and gate regions;

a plurality of parallel, elongated source pads extending from the source foot into electrical connection with the source regions respectively, the source pads crossing the gate foot in electrical isolation therefrom;

a plurality of parallel, elongated drain pads extending from the drain foot into electrical connection with the drain regions respectively;

a plurality of parallel, elongated gate fingers extending from the gate foot into electrical connection with the gate regions respectively; and

fixed tuning circuit means connected between the gate foot and the source foot, including;

an inductive stub having a first end connected to the gate foot and a second end; and

a capacitor having a first plate which is integral with the source foot and a second plate connected to the second end of the inductive stub.

2. An amplifier as in claim 1, in which the source pads include airbridge regions which extend over the gate foot in spaced relation therefrom.

3. An amplifier as in claim 1, in which:

the substrate has a first surface on which the source foot is formed and a second surface which is opposite to the first surface; and

the amplifier further comprises;

a ground plane formed on the second surface of the substrate; and

a via which extends through the substrate between the first and second surfaces and electrically connects the source foot to the ground plane.

4. An amplifier as in claim 1, in which the gate fingers are spaced closer to the source pads than to the drain pads.

5. A monolithic microwave integrated circuit (MMIC), comprising:

a substrate;

a plurality of parallel, elongated source and drain regions formed in the substrate in transverse alternating relation;

a plurality of elongated channel regions formed in the substrate between and parallel to adjacent source and drain regions respectively;

each adjacent source, drain and gate region constituting a field-effect transistor (FET) amplifier cell;

an elongated source foot extending substantially perpendicular to the source regions on a first longitudinally spaced side of said cells;

an elongated drain foot extending substantially perpendicular to the drain regions on a second longitudinally spaced side of said cells which is opposite to said first side;

an elongated gate foot extending substantially perpendicular to the gate regions on said first side between the source foot and said cells;

a plurality of parallel, elongated source pads extending from the source foot into electrical connection with the source regions respectively, the source pads crossing the gate foot in electrical isolation therefrom;

a plurality of parallel, elongated drain pads extending from the drain foot into electrical connection with the drain regions respectively;

a plurality of parallel, elongated gate fingers extending from the gate foot into electrical connection with the gate regions respectively; and

fixed tuning circuit means connected between the gate foot and the source foot, including;

an inductive stub having a first end connected to the gate foot and a second end; and

a capacitor having a first plate which is integral with the source foot and a second plate connected to the second end of the inductive stub.

6. An integrated circuit as in claim 5, in which the source pads include airbridge regions which extend over the gate foot in spaced relation therefrom.

7. An integrated circuit as in claim 5, in which:

the substrate has a first surface on which the source foot is formed and a second surface which is opposite to the first surface; and

the integrated circuit further comprises;

a ground plane formed on the second surface of the substrate; and

a via which extends through the substrate between the first and second surfaces and electrically connects the source foot to the ground plane.

8. An integrated circuit as in claim 5, in which the gate fingers are spaced closer to the source pads than to the drain pads.

9. An integrated circuit as in claim 5, in which said cells are fabricated in a metal-semiconductor field-effect transistor (MESFET) amplifier configuration.

10. A distributed field-effect transistor (FET) amplifier, comprising:

a substrate;

a plurality of parallel, elongated source and drain regions formed in the substrate in transverse alternating relation;

a plurality of elongated channel regions formed in the substrate between and parallel to the adjacent source and drain regions respectively;

an elongated source foot extending substantially perpendicular to the source regions;

an elongated drain foot extending substantially perpendicular to the drain regions;

an elongated gate foot extending substantially perpendicular to the gate regions;

a plurality of parallel, elongated source pads extending from the source foot into electrical connection with the source regions respectively;

a plurality of parallel, elongated drain pads extending from the drain foot into electrical connection with the drain regions respectively;

a plurality of parallel, elongated gate fingers extending from the gate foot into electrical connection with the gate regions respectively; and

fixed tuning circuit means connected between the gate foot and the source foot, including;

an inductive stub having a first end connected to the gate foot and a second end; and

a capacitor having a first plate which is integral with the source foot and a second plate connected to the second end of the inductive stub.

11. An amplifier as in claim 10, in which the source pads include airbridge regions which extend over the gate foot in spaced relation therefrom.

12. An amplifier as in claim 10, in which:

the substrate has a first surface on which the source foot is formed and a second surface which is opposite to the first surface; and

the amplifier further comprises;

a ground plane formed on the second surface of the substrate; and

a via which extends through the substrate between the first and second surfaces and electrically connects the source foot to the ground plane.

13. An amplifier as in claim 10, in which the gate fingers are spaced closer to the source pads than to the drain pads.