Semiconductor on insulator transistor

• US 5,283,457 A
• Filed: 03/05/1991
• Issued: 02/01/1994
• Est. Priority Date: 10/02/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Matloubian, Mishel
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US07/665,925
• Time in Patent Office: 1,064 Days
• Field of Search: 357/42, 357/23.7, 257/351, 257/369, 257/401
• US Class Current: 257/351
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor.

In a preferred embodiment, the channel of the main transistor is used as the source of the channel transistor and the gate of the main transistor extends onto the channel region of the channel transistor. The reference voltage is then connected to the drain region which is formed on the opposite side of the channel transistor channel region from the main transistor'"'"'s channel.

Claims

1. A transistor structure comprising:

a semiconductor layer having a first conductivity type;

a first drain region formed in said semiconductor layer, said first drain region having a second conductivity type;

a first source region formed in said semiconductive layer, said first source region having said second conductivity type, said first source region being separated from said first drain region by a first channel region;

a second channel region having said second conductivity type formed in said semiconductive layer abutting said first channel region and disposed perpendicularly to said first channel region;

a second drain region formed in said semiconductive layer, said second drain region having said first conductivity type, said second drain region being separated from said first channel region by said second channel region; and

a T-shaped gate formed on the surface of said semiconductive layer over said first and second channel regions such that a first potential applied to said gate causes said first channel region to be conductive and said second channel region to be non conductive and such that a second potential applied to said gate causes said second channel region to be substantially conductive and to couple said first channel region to a reference potential.

2. A transistor structure as in claim 1 wherein said semiconductive layer is formed on an insulating layer.

3. A transistor structure as in claim 2 wherein said insulating layer comprises silicon dioxide.

4. A transistor structure as in claim 1 wherein said gate is separated from said first and second channel regions by a gate dielectric layer.

5. A transistor structure as in claim 4 wherein said gate dielectric layer comprises silicon dioxide.

6. A transistor structure comprising:

a semiconductive layer having a first conductivity type;

a first drain region formed in said semiconductive layer, said first drain region having a second conductivity type;

a first source region formed in said semiconductive layer, said first source region having said second conductivity type, said first source region being separated from said first drain region by a first channel region;

a second source region formed in said semiconductive layer, said second source region having said first conductivity type and said second source region abutting said first channel region;

a second channel region having said second conductivity type formed in said semiconductive layer abutting said second source region, said second channel region disposed perpendicularly to said first channel region;

a second drain region formed in said semiconductive layer, said second drain region having said first conductivity type, said second drain region being separated from said first channel region by said second channel region; and

a T-shaped gate formed on the surface of said semiconductive layer over said first and second channel regions such that a first potential applied to said gate causes said first channel region to be conductive and said second channel region to be non conductive and such that a second potential applied to said gate causes said second channel region to be substantially conductive and to couple said first channel region to a reference potential.

7. A transistor structure as in claim 6 wherein said semiconductive layer is formed on an insulating layer.

8. A transistor structure as in claim 7 wherein said insulating layer comprises silicon dioxide.

9. A transistor structure as in claim 6 wherein said gate is separated from said first and second channel regions by a gate dielectric layer.

10. A transistor structure as in claim 9 wherein said gate dielectric layer comprises silicon dioxide.