One-time-programmable EEPROM cell

• US 5,283,759 A
• Filed: 06/18/1992
• Issued: 02/01/1994
• Est. Priority Date: 06/26/1991
• Status: Expired due to Term

• Current Assignee: Eurosil Electronic GmbH
• Original Assignee: Eurosil Electronic GmbH
• Inventors: Smith, Stuart
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): YOO, DO H
• Application Number:
  US07/900,482
• Time in Patent Office: 593 Days
• Field of Search: 365/104, 365/185
• US Class Current: 365/185.04
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM

Abstract

The invention relates to a one-time-programmable read-only memory cell, abbreviated as PROM. According to the prior art, PROM cells are programmed by the deliberate destruction of a component. Since the information is burnt into the memory cell in this way, a PROM cell can only be programmed once. If read-only memory cells are to be electrically programmed and cleared several times, floating gate transistors in particular are used. With the floating gate transistor, the information is stored as a charge on a completely insulated gate electrode. If PROM and EEPROM memory cells are now integrated on a common chip, this requires additional circuitry due to the different voltage requirements of the two different memory cells. In accordance with the invention, a repeatedly electrically programmable read-only memory is connected such that it can only be electrically programmed once.

Claims

1. A one-time electrically programmable read-only memory comprising:

a floating gate MOS transistor serving as a physical memory element and having a source connection, a drain connection, a bulk connection and a control gate connection, with said control gate and said bulk connections being connected to a common line for a programming voltage (VPP), and circuit means for supplying the drain connection of said floating gate transistor with a supply voltage during programming, with said circuit means comprising a series circuit of a first and a second MOS transistor connected between said drain connection and a supply voltage terminal and having respective control gates for receiving respective control signals.

2. A circuit array having a one-time electrically programmable read-only memory according to claim 1, wherein an array of EEPROM cells is provided, wherein the programming voltage (VPP) is supplied to said EEPROM cells via a circuit component controlled by said one-time electrically programmable read-only memory, and said one-time electrically programmable read-only memory is in the programmed state.

3. A one-time electrically programmable read-only memory according to claim 1 wherein said first and second MOS transistors have the same channel conductivity type.

4. A one-time electrically programmable read-only memory according to claim 3 wherein said first and second MOS transistors are p-channel transistors.

5. A one-time electrically programmable read-only memory according to claim 1 further comprising further circuit means for selectively preventing programming of said floating gate transistor when said first and second transistors are conductive, with said further circuit means including at least one further MOS transistor connecting said drain connection of said floating gate transistor to said common line for a programming voltage (VPP).

6. A one-time electrically programmable read-only memory according to claim 5 wherein said at least one further MOS transistor comprises third and fourth series connected MOS transistors having respective control gates for receiving respective control signals.

7. A one-time electrically programmable read-only memory according to claim 6 wherein said first and second MOS transistors are of the same channel conductivity type and said third and fourth MOS transistors are of the opposite channel conductivity type, and wherein one control gate of said first and second transistors and one control gate of said third and fourth transistors receive the same control signal.

8. A one-time electrically programmable read-only memory according to claim 7 wherein said first and second transistors are p-channel transistors and said third and forth transistors are n-channel transistors.

9. A one-time electrically programmable read-only memory according to claim 8 further comprising circuit means for reading the floating gate transistor including a fifth MOS transistor having a source-drain path connecting said supply voltage terminal, and a sixth MOS transistor having a source-drain path connecting the source connection of said floating gate transistor to said common line, with said fifth and sixth transistors each being responsive to a control signal at its control gate to render same conductive during read out.

10. A one-time electrically programmable read-only memory according to claim 9 wherein said fifth transistor is a p-channel transistor and said sixth transistor is an n-channel transistor.

11. A one-time electrically programmable read-only memory according to claim 1 further comprising circuit means for reading the floating gate transistor including a third MOS transistor having a source-drain path connecting said drain connection of said floating gate transistor to said supply voltage terminal, and a fourth MOS transistor having a source-drain path connecting the source connection of said floating gate transistor to said common line, with said third and fourth transistors each being responsive to a control signal at its control gate to render same conductive during read out.

12. A one-time electrically programmable read-only memory according to claim 11 wherein said third transistor is a p-channel transistor and said fourth transistor is an n-channel transistor.