Power up/power down controller and power fail detector for processor
First Claim
1. A power fail controller for detecting early failure of a power supply for providing power to a system having a processor and a volatile memory, comprising:
- an early power fail detection circuit for detecting a potential power supply failure in the power supply and generating a power fail signal for output to the processor;
an out of tolerance detection circuit for detecting when the power supply is out of tolerance in accordance with predetermined tolerance parameters and generating an out of tolerance signal for output to the processor;
a non-volatile memory accessible by the processor for storage of information therein, said information including executable instructions that are directly executable by the processor; and
an inhibit circuit for inhibiting the processor from accessing said non-volatile memory when said out of tolerance signal is generated.
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Accused Products
Abstract
A power fail control system for a CPU (10) and external memory (16) utilizes a controller (18). The controller (18) is operable to detect an early power fail situation and output an interrupt to the CPU (10). The CPU (10) then goes into a power down sequence and stores critical instructions in an internal memory array (30) constituting a hidden memory during the power down sequence. An out of tolerance detector detects when the power supply voltage has fallen below a predetermined threshold and then generates reset signal. The reset signal is input to the CPU (10) to indicate that no further instructions are executable. In addition, a Chip Enable switch (46) is operated to inhibit memory control signals from being transferred from the CPU (10) to the memory (16). The internal hidden memory (30) is also inhibited from having data written thereto in the presence of the reset signal. A backup battery (22) is provided which is connected to one side of a switch. The other side of the switch is connected to the power supply voltage. When the power supply voltage falls below the battery voltage, the battery is connected to supply a current to the external memory (16).
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Citations
40 Claims
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1. A power fail controller for detecting early failure of a power supply for providing power to a system having a processor and a volatile memory, comprising:
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an early power fail detection circuit for detecting a potential power supply failure in the power supply and generating a power fail signal for output to the processor; an out of tolerance detection circuit for detecting when the power supply is out of tolerance in accordance with predetermined tolerance parameters and generating an out of tolerance signal for output to the processor; a non-volatile memory accessible by the processor for storage of information therein, said information including executable instructions that are directly executable by the processor; and an inhibit circuit for inhibiting the processor from accessing said non-volatile memory when said out of tolerance signal is generated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A processor control system, comprising:
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a central processing unit for executing instructions within a predetermined address space; an external memory controlled by said central processing unit in response to memory control signals received from said central processing unit for access of data from said external memory by said central processing unit in a read mode and for transfer of data to said external memory from said central processing unit in a write mode; said central processing unit and said external memory each having a power supply associated therewith; and a power fail controller, including; a power fail detector for determining when said power supply associated with at least said central processing unit falls below a first threshold voltage, said power fail detector operable to generate a power fail signal in response to said power supply voltage associated with said central processing unit falling below said first threshold voltage, said power fail detector outputting said power fail signal to said central processing unit, said central processing unit operable to go into a power down sequence in response to receiving said power fail signal and continuing to execute instructions in said power down sequence, a non-volatile memory accessible by said central processing unit for storage of information including executable instructions therein in association with a predetermined portion of the predetermined address space associated with said central processing unit when said power fail signal is generated, and a mapping circuit for mapping said stored information in said non-volatile memory to said predetermined portion of said predetermined address space when said non-volatile memory is accessed. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A power fail controller for detecting early failure of a power supply for a central processing unit and an associated external memory, the central processing unit operable to execute instructions within a predetermined address space, comprising:
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an early power fail detection circuit for detecting a potential power supply failure in the power supply and generating a power fail signal for output to the central processing unit; the central processing unit operable to go into a power down sequence in response to receiving said power fail signal and continuing to execute instructions in said power down sequence; a non-volatile hidden memory for storing critical instructions including executable instructions; an access circuit for allowing the central processing unit to access said hidden memory when the central processing unit is in said power down sequence in response to generation of said power fail signal by said power fail detector; and said hidden memory occupying a predetermined portion of the address space associated with the central processing unit, said access circuitry operable to map said hidden memory in said predetermined portion of the address space associated with the central processing unit during said power down sequence of the central processing unit. - View Dependent Claims (24, 25, 26)
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27. A method for controlling operation of a central processing unit and an associated volatile external memory during power failure of an associated power supply, the central processing unit operable to execute instructions within a predetermined address space, comprising the steps of:
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detecting a potential power supply failure in the power supply and generating a power fail signal for output to the central processing unit in response to detecting the potential power supply failure; detecting when the power supply to at least the volatile external memory is out of tolerance relative to predetermined operating parameters of the volatile external memory and generating an out of tolerance signal in response to detecting when the power supply is out of tolerance; operating the central processing unit in a power down sequence when the power fail signal is generated and the out of tolerance signal is not generated; providing a non-volatile memory for storing critical information therein including executable instructions; and mapping the non-volatile memory to a predetermined portion of the predetermined address space during the power down sequence such that the executable instructions associated with the non-volatile memory are accessible by the central processing unit. - View Dependent Claims (28, 29, 30, 31, 32)
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33. A method for controlling operation of a central processing unit and an associated external memory that is controlled by the central processing unit in response to memory control signals received from the central processing unit, the central processing unit operable to execute instructions in a predetermined address space, the central processing unit and the associated external memory having a power supply associated therewith, comprising the steps of:
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determining when the voltage of the power supply associated with at least the central processing unit falls below a first threshold voltage and generating a power fail signal in response thereto for output to the central processing unit; the central processing unit operable to go into a power down sequence in response to receiving the power fail signal and continuing to execute instructions in the power down sequence; detecting when the voltage of the power supply associated with at least the external memory falls below a second threshold voltage and generating an out of tolerance signal in response thereto, the second threshold voltage being lower than the first threshold voltage; and inhibiting the writing of data to the external memory from the central processing unit in response to generation of the out of tolerance signal; providing a nonvolatile hidden memory for storing critical instructions including executable instructions utilized by the central processing unit; and mapping the nonvolatile hidden memory to a predetermined portion of the predetermined address space when the central processing unit is in the power down sequence in response to generation of the power fail signal such that the executable instructions stored in the nonvolatile memory are accessible by the central processing unit. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40)
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Specification