Method and apparatus for avoiding processor deadly embrace in a multiprocessor system

• US 5,283,870 A
• Filed: 10/04/1991
• Issued: 02/01/1994
• Est. Priority Date: 10/04/1991
• Status: Expired due to Term

• Current Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Original Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Inventors: Keeley, James W., Joyce, Thomas F.
• Primary Examiner(s): Evans, Arthur G.
• Assistant Examiner(s): Smith, Diane
• Application Number:
  US07/771,296
• Time in Patent Office: 851 Days
• Field of Search: 395/800, 395/200, 395/375, 364/241.8, 364/242.91, 364/252.4, 364/927.96, 364/927.97
• US Class Current: 711/152
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 9/524 Deadlock detection or avoidance

Abstract

A multiprocessor system includes a number of system processors which tightly couple to a system bus to share a main or system memory and a number of on-board memory processors which also are tightly coupled to the system bus. Each processor has a high performance microprocessor which tightly couples to an on-board or local memory through the microprocessor'"'"'s local bus. System memory is accessible using a memory lock protocol while the local memory is accessible through a bus lock protocol. Each on-board memory processor includes a lock mechanism which enables the processing of memory lock commands directed to its local memory received via the system bus from any other processor and for issuing memory lock commands to system memory.

Claims

1. A multiprocessor system comprising a system memory, a number of system processors and a number of peer processors, each processor being tightly coupled according to a first protocol and a system memory, each of said peer processors comprising;

a microprocessor;

an on-board local memory;

a synchronous local bus connected for tightly coupling said microprocessor and said local memory together to operate according to a second protocol; and

, bus interface circuits coupled to said system bus and to said local bus, said bus interface circuits including;

first transfer means coupled to said system bus and to said synchronous bus for transferring requests of said each of said peer processors received from any one of said system processors and other ones of said peer processors;

second transfer means coupled to said system bus and to said synchronous local bus for transferring requests generated by said microprocessor to said system bus according to said second protocol for reading and writing said system memory or said local memory of another one of said peer processors;

system bus response means coupled to said system bus for generating responses to requests transmitted to or received from said system bus, said response means including on-board memory lock indicator means coupled to said system bus; and

,

processor system lock indicator means coupled to said system bus, to said second transfer means and to said system bus response means;

said on-board memory lock indicator being set in response to each memory read lock command generated by one of said processors and received from said system bus which is used for performing a read-modify-write operation on an item of information stored in said local memory in response to each memory read lock command, said first transfer means generating an output signal on said local bus to said microprocessor for inhibiting further accesses by said microprocessor to said local memory until completion of said read-modify-write operation by said local memory; and

,

said processor lock indicator means being set in response to a first microprocessor memory read lock request transferred to said system bus by said second transfer means and acknowledged by said system bus response means of a specified one of said peer processors, said processor indicator means when set generating an output lock signal for inhibiting said second transfer means from transferring any further microprocessor memory read lock requests to said system bus until completion of said first read lock request thereby preventing a possibility of a deadlock condition in accessing said on-board local memories of said peer processors.

2. The system of claim 1 wherein said second transfer means converts each microprocessor memory read lock command subsequently received from said microprocessor during the completion of said first read lock request into a normal read command.

3. The system of claim 1 wherein said output signal from said on-board memory lock indicator causes said system bus response means to signal non acceptance of each subsequent memory lock request received from said system bus until the completion of said microprocessor memory read lock command.

4. The system of claim 1 wherein said said second protocol used to access local memory is a synchronous bus protocol.

5. The system of claim 1 wherein said first protocol used to access said system bus is a memory bus protocol.

6. The system of claim 1 wherein said first transfer means includes first conversion means for converting each of said memory read lock commands received from said system bus into a memory read lock bus command consistent with said second protocol.

7. The system of claim 1 wherein said second transfer means includes second conversion means for converting each of said microprocessor memory read lock commands into commands which utilize said first protocol.

8. The system of claim 1 wherein said second conversion means converts a first write command following said first memory read lock command received from said microprocessor into a write clear command.

9. The system of claim 8 wherein said processor lock indicator means in response to said write clear command received from said system bus switches to a reset state enabling said peer processor to accept further system memory lock commands from said system bus.

10. The system of claim 7 wherein said first protocol utilizes a split bus cycle mode of operation.