Method of fast buffer copying by utilizing a cache memory to accept a page of source buffer contents and then supplying these contents to a target buffer without causing unnecessary wait states
First Claim
1. In a computer system having a microprocessor having a plurality of registers, main memory utilizing paged mode memory devices, a memory controller, a cache memory and a cache memory controller, an improved method for copying information from a first buffer beginning at a first address in main memory, the first buffer having a size less than that of the cache memory, to a second buffer beginning at a second address in main memory, the steps comprising:
- (a) reading n bytes from the first buffer, where n is a word width;
(b) writing said n bytes to a location which does not result in a page miss of the paged mode memory devices and simultaneously writing said n bytes into the cache memory;
(c) performing steps (a) through (b) as a series of page hit read operations of the paged mode memory devices until the contents of the first buffer have been loaded into cache memory;
(d) reading n bytes of the first buffer from the cache memory;
(e) writing said n bytes to the second buffer address; and
(f) performing steps (d) through (e) as a series of cache read hits and page write hits to the paged mode memory devices until the contents of the first buffer have been written from the cache memory to the second buffer.
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Accused Products
Abstract
A method for performing buffer copy operations in a personal computer system utilizing paged memory mode architecture and having a cache memory. The contents of a first buffer are read into a microprocessor register and simultaneously written into a cache memory. The first buffer is then read again and written to a second buffer, with the actual data values being obtained from the cache memory. This method avoids excessive wait states associated with changing memory pages from the first buffer memory address to the second buffer memory address for each data value.
23 Citations
7 Claims
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1. In a computer system having a microprocessor having a plurality of registers, main memory utilizing paged mode memory devices, a memory controller, a cache memory and a cache memory controller, an improved method for copying information from a first buffer beginning at a first address in main memory, the first buffer having a size less than that of the cache memory, to a second buffer beginning at a second address in main memory, the steps comprising:
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(a) reading n bytes from the first buffer, where n is a word width; (b) writing said n bytes to a location which does not result in a page miss of the paged mode memory devices and simultaneously writing said n bytes into the cache memory; (c) performing steps (a) through (b) as a series of page hit read operations of the paged mode memory devices until the contents of the first buffer have been loaded into cache memory; (d) reading n bytes of the first buffer from the cache memory; (e) writing said n bytes to the second buffer address; and (f) performing steps (d) through (e) as a series of cache read hits and page write hits to the paged mode memory devices until the contents of the first buffer have been written from the cache memory to the second buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification