Hardware based interface for mode switching to access memory above one megabyte

• US 5,283,889 A
• Filed: 03/11/1993
• Issued: 02/01/1994
• Est. Priority Date: 12/29/1989
• Status: Expired

• Current Assignee: NEC Corporation
• Original Assignee: Zenith Data Systems Corp. (Acer, Inc.)
• Inventors: Gauthier, Lloyd, Kohtz, Robert A., DeLisle, David J., Fakhruddin, Saifee
• Primary Examiner(s): Anderson, Lawrence E.
• Assistant Examiner(s): GECKIL, MEHMET B
• Application Number:
  US08/031,029
• Time in Patent Office: 327 Days
• Field of Search: 395/500, 395/400, 395/425, 395/275, 395/725, 364/189, 341/22
• US Class Current: 703/24
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.

Claims

1. A computer system comprising:

a central processing unit (CPU) for processing data adapted to be coupled to one or more peripheral devices by way of a predetermined keyboard interface, said CPU having at least two modes of operation including a real mode of operation for accessing memory up to one megabyte, said mode of accessing memory above one megabyte, said mode of operation adapted to be selected by one or more predetermined control signals, said CPU adapted to be reset by way of a predetermined reset signal;

a memory for storing data, said memory having a preselected number of addressable storage locations larger than one megabyte, said storage locations being selectable by at least twenty-one address lines A0-A20, said memory and said CPU connected to a common bus;

means for enabling said A20 address line for memory accesses over one megabyte in response to a hardware based Gate A20 control signal;

a system control processor (SCF) for communicating with said CPU and adapted to generate the reset signal for resetting said CPU under predetermined conditions; and

interfacing means interconnected between said CPU and said SCP for interfacing said CPU and said SCP for controlling communication between said CPU and said SCP and for emulating said predetermined keyboard interface, said interfacing means including predetermined hardware for enabling switching the mode of operation of said CPU from said real mode of operation to said protected mode of operation and for generating the hardware based Gate A20 signal for enabling said CPU to access memory above one megabyte by automatically enabling said A20 address line in response to said hardware based Gate A20 control signal, said interfacing means further including means for enabling either said SCP or said CPU to generate said reset signal.

2. A computer system as recited in claim 1, further including means for allowing said CPU to control memory accesses above one megabyte without interrupting said SCP and means for disabling said allowing means under predetermined conditions.

3. A computer system as recited in claim 1, further including means for allowing said SCP to control memory accesses above one megabyte.

4. A computer system as recited in claim 1, wherein said computer system further includes external memory other than said memory larger than one megabyte and said interfacing means includes first access means for accessing said external memory.

5. A computer system as recited in claim 1, further including one or more parts for allowing said CPU to communicate with external devices and second access means for accessing said ports.

6. A computer system as recited in claim 1, further including a mouse and wherein said interfacing means includes means for supporting said mouse.