Hardware based interface for mode switching to access memory above one megabyte
First Claim
1. A computer system comprising:
- a central processing unit (CPU) for processing data adapted to be coupled to one or more peripheral devices by way of a predetermined keyboard interface, said CPU having at least two modes of operation including a real mode of operation for accessing memory up to one megabyte, said mode of accessing memory above one megabyte, said mode of operation adapted to be selected by one or more predetermined control signals, said CPU adapted to be reset by way of a predetermined reset signal;
a memory for storing data, said memory having a preselected number of addressable storage locations larger than one megabyte, said storage locations being selectable by at least twenty-one address lines A0-A20, said memory and said CPU connected to a common bus;
means for enabling said A20 address line for memory accesses over one megabyte in response to a hardware based Gate A20 control signal;
a system control processor (SCF) for communicating with said CPU and adapted to generate the reset signal for resetting said CPU under predetermined conditions; and
interfacing means interconnected between said CPU and said SCP for interfacing said CPU and said SCP for controlling communication between said CPU and said SCP and for emulating said predetermined keyboard interface, said interfacing means including predetermined hardware for enabling switching the mode of operation of said CPU from said real mode of operation to said protected mode of operation and for generating the hardware based Gate A20 signal for enabling said CPU to access memory above one megabyte by automatically enabling said A20 address line in response to said hardware based Gate A20 control signal, said interfacing means further including means for enabling either said SCP or said CPU to generate said reset signal.
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Abstract
A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.
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Citations
6 Claims
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1. A computer system comprising:
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a central processing unit (CPU) for processing data adapted to be coupled to one or more peripheral devices by way of a predetermined keyboard interface, said CPU having at least two modes of operation including a real mode of operation for accessing memory up to one megabyte, said mode of accessing memory above one megabyte, said mode of operation adapted to be selected by one or more predetermined control signals, said CPU adapted to be reset by way of a predetermined reset signal; a memory for storing data, said memory having a preselected number of addressable storage locations larger than one megabyte, said storage locations being selectable by at least twenty-one address lines A0-A20, said memory and said CPU connected to a common bus; means for enabling said A20 address line for memory accesses over one megabyte in response to a hardware based Gate A20 control signal; a system control processor (SCF) for communicating with said CPU and adapted to generate the reset signal for resetting said CPU under predetermined conditions; and interfacing means interconnected between said CPU and said SCP for interfacing said CPU and said SCP for controlling communication between said CPU and said SCP and for emulating said predetermined keyboard interface, said interfacing means including predetermined hardware for enabling switching the mode of operation of said CPU from said real mode of operation to said protected mode of operation and for generating the hardware based Gate A20 signal for enabling said CPU to access memory above one megabyte by automatically enabling said A20 address line in response to said hardware based Gate A20 control signal, said interfacing means further including means for enabling either said SCP or said CPU to generate said reset signal. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification