Cache memory arrangement with write buffer pipeline providing for concurrent cache determinations
First Claim
1. A cache memory arrangement comprising:
- an array of Random Access Memory (RAM) for caching information, said RAM having an address input, a data input, a write enable input, and a data output;
address buffer means having an address buffer input and an address buffer output, said address buffer output coupled to said address input of said RAM;
data buffer means having a data buffer input and a data buffer output, said data buffer output coupled to said data input of said RAM;
circuit means for determining whether a cache hit or miss has occured in response to an access directed to said RAM;
control circuit means, coupled to said array of RAM and said circuit means, for selectively coupling write enable signals to said array of RAM;
wherein an address transferred to said address buffer input is transferred from said address buffer input to said address buffer output while said circuit means determines whether a cache hit or miss has occurred;
further wherein, data transferred to said address data input is transferred from said data buffer input to said data buffer output while said circuit means determines whether a cache hit or miss has occurred.
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Accused Products
Abstract
A cache memory is arranged using write buffering circuitry. This cache memory arrangement comprises a Random Access Memory (RAM) array for memory storage operated under the control of a control circuit which receives input signals representing address information, write control signals, and write cancel signals. At least one address register buffer is coupled to the address input of the RAM, while at least one data register buffer is coupled to the data input of the RAM. Thus, in accordance with the present invention, addresses to be accessed in the RAM, as well as data to be written to the RAM, are buffered prior to being coupled to the RAM. As a result, systems utilizing the cache memory arrangement of the present invention need not stall or delay the output of information toward the RAM in order to check for a cache hit or miss. Such determinations can advantageously be made while the relevant address and data are in the register buffers en route to the RAM. Any write cancels necessitated by a cache miss then abort the write prior to the coupling of the write address and data to the RAM.
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Citations
12 Claims
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1. A cache memory arrangement comprising:
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an array of Random Access Memory (RAM) for caching information, said RAM having an address input, a data input, a write enable input, and a data output; address buffer means having an address buffer input and an address buffer output, said address buffer output coupled to said address input of said RAM; data buffer means having a data buffer input and a data buffer output, said data buffer output coupled to said data input of said RAM; circuit means for determining whether a cache hit or miss has occured in response to an access directed to said RAM; control circuit means, coupled to said array of RAM and said circuit means, for selectively coupling write enable signals to said array of RAM; wherein an address transferred to said address buffer input is transferred from said address buffer input to said address buffer output while said circuit means determines whether a cache hit or miss has occurred; further wherein, data transferred to said address data input is transferred from said data buffer input to said data buffer output while said circuit means determines whether a cache hit or miss has occurred.
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2. A cache memory arrangement comprising:
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an array of Random Access Memory (RAM) for caching information, said RAM having an address input, a data input, a write enable input, and a data output; a control circuit coupled to said array of RAM, said control circuit including means for selectively coupling write enable signals to said RAM; a first register coupled to said address input of said RAM; a second register coupled to said data input of said RAM; a third register coupled to said first register; a fourth register coupled to second register; a fifth register coupled to said third register; a sixth register coupled to fourth register; a first comparator circuit, said first comparator circuit including a first comparator input, a second comparator input, and a first comparator output; wherein said first, third, and fifth registers provide for address buffering, and said second, fourth, and sixth registers provide for data buffering in said cache memory arrangement; and further wherein said first comparator input is coupled to said first register, said second comparator input is coupled to said fifth register, and said first comparator output is coupled to a means for receiving address information in said control circuit. - View Dependent Claims (3, 4, 5, 6)
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7. In a computer system comprising cache memory, said cache memory having a data input and an address input, a method for obviating the need to delay a write operation to said cache memory to determine whether a cache hit or miss has occurred prior to outputting information associated with said write operation, said method comprising the steps:
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transferring an address associated with said write operation directed to said cache memory to an address buffer; transferring data associated with said write operation directed to said cache memory to a data buffer; determining whether a cache hit or miss has occurred for said write operation directed to said cache memory while said address is in said address buffer and said data is in said data buffer such that said computer system does not halt to make said determination; enabling said cache memory to read said address from said address buffer and said data from said data buffer in the event of a cache hit. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification