Cache memory arrangement with write buffer pipeline providing for concurrent cache determinations

• US 5,283,890 A
• Filed: 02/02/1993
• Issued: 02/01/1994
• Est. Priority Date: 04/30/1990
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Brown, Emil W. III, Petolino, Joseph A. Jr.
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): Elmore, Reba I.
• Application Number:
  US08/012,621
• Time in Patent Office: 364 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/400 MS File, 395/425 MS File
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence

Abstract

A cache memory is arranged using write buffering circuitry. This cache memory arrangement comprises a Random Access Memory (RAM) array for memory storage operated under the control of a control circuit which receives input signals representing address information, write control signals, and write cancel signals. At least one address register buffer is coupled to the address input of the RAM, while at least one data register buffer is coupled to the data input of the RAM. Thus, in accordance with the present invention, addresses to be accessed in the RAM, as well as data to be written to the RAM, are buffered prior to being coupled to the RAM. As a result, systems utilizing the cache memory arrangement of the present invention need not stall or delay the output of information toward the RAM in order to check for a cache hit or miss. Such determinations can advantageously be made while the relevant address and data are in the register buffers en route to the RAM. Any write cancels necessitated by a cache miss then abort the write prior to the coupling of the write address and data to the RAM.

Claims

1. A cache memory arrangement comprising:

an array of Random Access Memory (RAM) for caching information, said RAM having an address input, a data input, a write enable input, and a data output;

address buffer means having an address buffer input and an address buffer output, said address buffer output coupled to said address input of said RAM;

data buffer means having a data buffer input and a data buffer output, said data buffer output coupled to said data input of said RAM;

circuit means for determining whether a cache hit or miss has occured in response to an access directed to said RAM;

control circuit means, coupled to said array of RAM and said circuit means, for selectively coupling write enable signals to said array of RAM;

wherein an address transferred to said address buffer input is transferred from said address buffer input to said address buffer output while said circuit means determines whether a cache hit or miss has occurred;

further wherein, data transferred to said address data input is transferred from said data buffer input to said data buffer output while said circuit means determines whether a cache hit or miss has occurred.

2. A cache memory arrangement comprising:

an array of Random Access Memory (RAM) for caching information, said RAM having an address input, a data input, a write enable input, and a data output;

a control circuit coupled to said array of RAM, said control circuit including means for selectively coupling write enable signals to said RAM;

a first register coupled to said address input of said RAM;

a second register coupled to said data input of said RAM;

a third register coupled to said first register;

a fourth register coupled to second register;

a fifth register coupled to said third register;

a sixth register coupled to fourth register;

a first comparator circuit, said first comparator circuit including a first comparator input, a second comparator input, and a first comparator output;

wherein said first, third, and fifth registers provide for address buffering, and said second, fourth, and sixth registers provide for data buffering in said cache memory arrangement;

and further wherein said first comparator input is coupled to said first register, said second comparator input is coupled to said fifth register, and said first comparator output is coupled to a means for receiving address information in said control circuit.

3. The cache memory arrangement as provided in claim 2, further comprising:

a second comparator circuit, said second comparator circuit including a third comparator input, a fourth comparator input, and a second comparator output;

wherein said third comparator input is coupled to said third register, said second comparator input is coupled to said fifth register, and said second comparator output is coupled to said means for receiving address information in said control circuit.

4. The cache memory arrangement as provided in claim 3, further comprising:

a first multiplexer, said first multiplexer including a first multiplexer input, a second multiplexer input, and a first multiplexer output;

wherein said first multiplexer input is coupled to said first register, said second multiplexer input is coupled to said fifth register, and said first multiplexer output is coupled to said address input of said RAM such that said first multiplexer is disposed between said first register and said address input of said RAM.

5. The cache memory arrangement as provided in claim 4, further comprising:

a second multiplexer, said second multiplexer including a third multiplexer input, a fourth multiplexer input, and a second multiplexer output;

wherein said second multiplexer input is coupled to said second register, said fourth multiplexer input is coupled to said sixth register, and said second multiplexer output is coupled to said data input of said RAM such that said second multiplexer is disposed between said second register and said data input of said RAM.

6. The cache memory arrangement as provided in claim 5, further comprising:

a third multiplexer, said third multiplexer including a fifth multiplexer input, a sixth multiplexer input, and a third multiplexer output;

wherein said fifth multiplexer input is coupled to said data input of said RAM, and said sixth multiplexer input is coupled to said data output of said RAM.

7. In a computer system comprising cache memory, said cache memory having a data input and an address input, a method for obviating the need to delay a write operation to said cache memory to determine whether a cache hit or miss has occurred prior to outputting information associated with said write operation, said method comprising the steps:

transferring an address associated with said write operation directed to said cache memory to an address buffer;

transferring data associated with said write operation directed to said cache memory to a data buffer;

determining whether a cache hit or miss has occurred for said write operation directed to said cache memory while said address is in said address buffer and said data is in said data buffer such that said computer system does not halt to make said determination;

enabling said cache memory to read said address from said address buffer and said data from said data buffer in the event of a cache hit.

8. The method as provided in claim 7, wherein said data buffer comprises a first register having a first register input and a first register output wherein,

said step of transferring data associated with said write operation comprises transferring said data to said first register input;

said step of determining whether a cache hit or miss has occurred for said write operation while said address is in said address buffer and said data is in said data buffer comprises determining whether said cache hit or miss has occurred while said data is being transferred from said first register input to said first register output;

said step of enabling said cache memory to read said address from said address buffer and said data from said data buffer in the event of a cache hit comprises enabling said cache memory to read said data from said first register output.

9. The method as provided in claim 8, wherein said address buffer comprises a second register having a second register input and a second register output wherein,

said step of transferring an address associated with said write operation comprises transferring said address to said second register input;

said step of determining whether a cache hit or miss has occurred for said write operation while said address is in said address buffer and said data is in said data buffer comprises determining whether said cache hit or miss has occurred while said address is being transferred from said second register input to said second register output;

said step of enabling said cache memory to read said address from said address buffer and said data from said data buffer in the event of a cache hit comprises enabling said cache memory to read said address from said first register output.

10. The method as provided in claim 7, wherein said data buffer comprises a first plurality of registers having a first plurality of registers input and a first plurality of registers output wherein,

said step of coupling an address associated with said write operation comprises transferring said address to said first plurality of registers input;

said step of determining whether a cache hit or miss has occurred for said write operation while said address is in said address buffer and said data is in said data buffer comprises determining whether said cache hit or miss has occurred while said address is being transferred from said first plurality of registers input to said first plurality of registers output;

said step of enabling said cache memory to read said address from said address buffer and said data from said data buffer in the event of a cache hit comprises enabling said cache memory to read said address from said first plurality of registers output.

11. The method as provided in claim 10, wherein said address buffer comprises a second plurality of registers having a second plurality of registers input and a second plurality of registers output wherein,

said step of transferring an address associated with said write operation comprises transferring said address to said second plurality of registers input;

said step of determining whether a cache hit or miss has occurred for said write operation while said address is in said address buffer and said data is in said data buffer comprises determining whether said cache hit or miss has occurred while said address is being transferred from said second plurality of registers input to said second plurality of registers output;

said step of enabling said cache memory to read said address from said address buffer and said data from said data buffer in the event of a cache hit comprises enabling said cache memory to read said address from said second plurality of registers output.

12. The method as provided in claim 7, further comprising the following step:

in the event of a cache miss for said write operation, not enabling said cache memory to read the data and addresses associated with said write operation from said data buffer and said address buffer, such that the data and addresses associated with said write operation are not written to a location in the cache memory.