Multi-processor programmable interrupt controller system
First Claim
1. A multi-processor programmable controller system for operation in a multi-processor environment that includes a multiplicity of processors and at least one peripheral unit interconnected by a common multi-processor system bus, wherein the peripheral unit has an interrupt request line that may signal a request for servicing from at least one processor and, wherein any processor may request service from any other processor using an interrupt bus without the use of the common multi-processor system bus, comprising:
- a) an interrupt bus for communicating interrupt request and interrupt request status messages;
b) an I/O controller connected to the interrupt request line of at least one associated peripheral and the interrupt bus, for accepting at least one peripheral interrupt signal, for formatting the interrupt signals for transmission on said interrupt bus, the formatted signal being representative of the nature and priority of the peripheral interrupt signal, and indicative of the group of processors eligible to service the interrupt, for transmitting the formatted interrupt signals and for receiving status information on the disposition of the interrupt request;
c) a multiplicity of local processor controllers, each local processor controller associated with a specific processor, each local processor controller comprising means for accepting processor interrupt request signals from the associated processor, means for formatting the associated processor interrupt request signals, the formatted associated processor interrupt signals being indicative of the nature and priority of the associated processor interrupt, connected to said interrupt bus for receiving and accepting both I/O controller and other local processor controller formatted interrupt signals for which its associated processor is eligible to service, means for transmitting the associated processor formatted interrupt signals on said interrupt bus, means for broadcasting on said interrupt bus an acceptance signal upon acceptance of the received interrupt signals, means for queuing the accepted interrupt signals, and means for delivering accepted interrupts to the associated processor for servicing in priority order.
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Abstract
A multi-processor programmable interrupt controller system which includes: an I/O interrupt controller for receiving interrupt requests from an I/O subsystem; multiple processor interrupt controllers, each associated with a specific processor for dispensing of accepted interrupts; and an interrupt controller bus primarily for the transmission of interrupt requests between interrupt controller units and for priority arbitration, using a standard message format and arbitration protocol.
388 Citations
18 Claims
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1. A multi-processor programmable controller system for operation in a multi-processor environment that includes a multiplicity of processors and at least one peripheral unit interconnected by a common multi-processor system bus, wherein the peripheral unit has an interrupt request line that may signal a request for servicing from at least one processor and, wherein any processor may request service from any other processor using an interrupt bus without the use of the common multi-processor system bus, comprising:
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a) an interrupt bus for communicating interrupt request and interrupt request status messages; b) an I/O controller connected to the interrupt request line of at least one associated peripheral and the interrupt bus, for accepting at least one peripheral interrupt signal, for formatting the interrupt signals for transmission on said interrupt bus, the formatted signal being representative of the nature and priority of the peripheral interrupt signal, and indicative of the group of processors eligible to service the interrupt, for transmitting the formatted interrupt signals and for receiving status information on the disposition of the interrupt request; c) a multiplicity of local processor controllers, each local processor controller associated with a specific processor, each local processor controller comprising means for accepting processor interrupt request signals from the associated processor, means for formatting the associated processor interrupt request signals, the formatted associated processor interrupt signals being indicative of the nature and priority of the associated processor interrupt, connected to said interrupt bus for receiving and accepting both I/O controller and other local processor controller formatted interrupt signals for which its associated processor is eligible to service, means for transmitting the associated processor formatted interrupt signals on said interrupt bus, means for broadcasting on said interrupt bus an acceptance signal upon acceptance of the received interrupt signals, means for queuing the accepted interrupt signals, and means for delivering accepted interrupts to the associated processor for servicing in priority order. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A multi-processor programmable interrupt controller system for operation in a multi-processor environment that includes at least one peripheral unit, wherein the peripheral unit has an interrupt request line that may signal a request for servicing from at least one processor and wherein any processor may request service from any other processor using an interrupt bus without the use of a common multi-processor system bus, each processor having a data/address bus, the multi-processor programmable controller system comprising:
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a) an interrupt controller bus, distinct from the multi-processor system bus, for communicating interrupt request, interrupt request status, and interrupt controller bus arbitration messages; b) an I/O interrupt controller comprising; i) multiple interrupt signal input pins, each pin for connecting to a distinct interrupt request line for accepting I/O peripheral interrupt signals; ii) a processor programmable re-direction table connected to said input pins comprising means for decoding I/O peripheral interrupt signals, means for prioritizing, means for destination addressing, and an output for outputting the decoded I/O peripheral interrupt signals; and iii) interrupt controller bus send/receive means connected to said interrupt controller bus and to said re-direction table output, for transmitting and receiving interrupt controller bus messages and for arbitrating control of said interrupt controller bus; and c) each local processor interrupt controller connected to said interrupt controller bus and to the data/address bus of an associated local processor, comprising; i) send/receive means for receiving and sending interrupt, interrupt status, and arbitration related messages on said interrupt controller bus; ii) acceptance logic means for rejecting, accepting, and arbitrating received interrupt request messages including interrupt type and priority information; iii) recording means coupled to said acceptance logic means and said send/receive means for recording the status of accepted interrupt request messages including type and priority; iv) nesting storage means for priority ordering (nesting) of the accepted interrupt requests, connected to the local processor data/address bus, for storing and delivering the highest priority interrupt request when its associated local processor'"'"'s priority is less than the highest priority queued interrupt request, and for sending a delivery attempt accepted acknowledgment from the processor to the sending source via said interrupt controller bus; v) means for storing the processor controller identification number used for identifying each processor controller, coupled to the local processor data/address bus for processor assignment of the identification number, and coupled to said send/receive means and said acceptance logic means for use in arbitrating and accepting received interrupt request signals; vi) means for tracking the associated local processor'"'"'s current task priority and delivering same to said acceptance logic means; and vii) means coupled to the associated local processor and to said send/receive means for formatting an interrupt message specified by the associated local processor and for initiating transmission of the messages by said send/receive means. - View Dependent Claims (16, 17, 18)
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Specification