Global planarization process

• US 5,284,804 A
• Filed: 12/31/1991
• Issued: 02/08/1994
• Est. Priority Date: 12/31/1991
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Moslehi, Mehrdad M.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US07/816,458
• Time in Patent Office: 770 Days
• Field of Search: 437/22882, 437/238, 437/240, 437/195, 437/245, 437/246, 156/632, 156/653, 156/626, 156/627
• US Class Current: 438/698
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]

Abstract

A novel global planarization process is disclosed which is fully compatible with semiconductor processing. The process disclosed is called metal melt-solidification planarization (MMSP). A layer of a low melting point/high boiling point metal such as tin or a suitable alloy is deposited on a nonplanar wafer surface via physical-vapor deposition or chemical-vapor deposition or evaporation or plating. The wafer is then heated to above the tin melting point, cooled back to resolidify tin, and etched back to form a globally planar surface.

Claims

1. A method of planarizing a structure lying on a substrate comprising:

depositing a disposable planarization layer which is in solid form at room temperature;

forming a liquid melt from said planarization layer over the substrate so as to form a planar liquid melt surface;

solidifying said melt so as to form a planar solid layer;

etching back said planar solid layer to a predetermined level on said structure.

2. A method as recited in claim 1 wherein said liquid melt is formed from a material having greater surface tension forces than forces of viscosity.

3. A method as recited in claim 1 wherein said substrate is formed of semiconductor material.

4. A method of planarizing an interlevel dielectric layer on a substrate comprising:

placing an interlevel dielectric layer over said substrate;

placing an adhesion layer over said interlevel dielectric;

placing a planarization layer over said adhesion layer;

melting, planarizing and resolidifying said planarization layer via heating and cooling said substrate; and

etching-back said planarization layer into said interlevel dielectric layer so as to form a planar surface on said interlevel dielectric layer.

5. A method as recited in claim 4 wherein said etch-back is performed with an etch process including a 1-to-1 etchant selectivity as between said planarization layer and said interlevel dielectric layer.

6. A method as recited in claim 4 wherein a barrier layer is placed on said interlevel dielectric and said adhesion layer is placed over said barrier layer.

7. A method as recited in claim 6 wherein said barrier layer comprises Si₃ N₄ or silicon oxynitride.

8. A method as recited in claim 6 wherein said barrier layer is a plasma deposited silicon nitride material.

9. A method as recited in claim 4 wherein said interlevel dielectric is deposited over said substrate.

10. A method as recited in claim 4 wherein said interlevel dielectric layer comprises a dielectric selected from the group consisting of phosophosilicate glass or borophosphosilicate glass, undoped oxide or a combination thereof.

11. A method as recited in claim 4 wherein said adhesion layer comprises a material selected from the group consisting of titanium, silicon or aluminum.

12. A method as recited in claim 11 wherein said adhesion layer comprises a material selected from the group consisting of TiW or TiN.

13. A method as recited in claim 4 wherein said planarization layer is selected from the group consisting of tin, tin alloy, bismuth, bismuth alloy, indium, indium alloy, or a combination thereof.

14. A method as recited in claim 4 wherein said adhesion layer serves as a buffer against contaminants to said substrate.

15. A method as recited in claim 4 wherein said adhesion layer is deposited according to a method selected from the group consisting of physical-vapor deposition or chemical-vapor deposition.

16. A method as recited in claim 4 wherein said planarization layer is deposited over said adhesion layer according to a physical-deposition process or chemical-deposition process or an evaporation or plating process.

17. A method of planarizing an interlevel dielectric layer on a substrate comprising:

placing an interlevel dielectric layer over said substrate;

placing an adhesion layer over said interlevel dielectric;

placing a planarization layer over said adhesion layer;

melting, planarizing, and resolidifying said planarization layer via heating and cooling said substrate;

etching-back said planarization layer into said interlevel dielectric layer until detecting an etch-back end-point level.

18. A method as recited in claim 17 wherein said etch-back end-point level is detected using a method of measuring surface reflectance.

19. A method as recited in claim 17 wherein said etch-back end-point is detected using a method of measuring electrical sheet resistance.