Circuit for adjusting analog signal waveforms

• US 5,285,410 A
• Filed: 10/25/1991
• Issued: 02/08/1994
• Est. Priority Date: 01/18/1991
• Status: Expired due to Fees

• Current Assignee: Tomohiko Suzuki
• Original Assignee: Addams Systems Incorporated
• Inventors: Suzuki, Tomohiko
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/782,802
• Time in Patent Office: 837 Days
• Field of Search: 365/45, 341/55, 329/50
• US Class Current: 365/45
• CPC Class Codes: G11C 27/04 Shift registers

Abstract

Circuits for matching amplitudes and/or frequencies of analog signal waveforms stored in two analog signal delay elements (hereinbelow, ADMs) are desclosed. In order to equalize amplitudes of the analog signal waveforms stored in two ADMs, peak values of the amplitudes of the analog signal waveforms stored in the two ADMs are compared, then based on the comparison result, gain of an amplifier for amplifying or attenuating amplitudes of either one of the analog waveforms is controlled. In order to equalize frequencies of the analog signal waveforms stored in the two ADMs, a term of duration between adjacent peaks of the analog signal waveforms stored in the two ADMs are compared, and then based on the comparison result, the circulation speed of the analog signal waveform in one of the ADMs is controlled.

Claims

1. A circuit for adjusting analog signal waveforms to equalize amplitudes of two analog signal waveforms including:

first and second analog dynamic memory circuits each comprising a closed loop in which a first or a second analog signal waveform circulates, said closed loop including an analog signal waveform delay element comprising a series of charge storing cells,

a first peak detector which comprises a first diode group having a plurality of diodes which are connected in the normal-biased direction between the charge storing cells of the delay element of said first analog dynamic memory circuit and a common output connected to a bias voltage supply for detecting the peak value of the first analogs signal waveform stored at the common output of the first analog dynamic memory circuit;

a second peak detector comprising a second diode group having a plurality of diodes which are connected in the normal-biased direction between the charge storing cells of the delay element of said second analog dynamic memory circuit and a common output connected to a bias voltage supply for detecting the peak value of the second analog signal waveform at the common output of the second analog dynamic memory circuit;

a comparator having a first input connected to the common output of the first peak detector, a second input connected to the common output of the second peak detector and an output for outputting a signal representing a ratio of or a difference between the peak values inputted from the first and the second inputs; and

a variable gain amplifier having an input connected to the output of said comparator and provided in the closed loop of the first or the second analog dynamic memory circuit, a gain of the variable gain amplifier being varied according to the signal representing the ratio or the difference, thereby amplifying or attenuating the amplitude of the first or the second signal waveform.

2. A circuit for adjusting analog signal waveforms to equalize pitches of two analog signal waveforms including:

first and second analog dynamic memory circuits each comprising a closed loop in which a first or a second analog signal waveform circulates, said closed loop including an analog signal waveform delay element comprising a series of charge storing cells;

a first peak detector having a first diode connected in the normal-biased direction between one of the charge storing cells of the delay element of the first analog dynamic memory circuit and a bias power supply, the end of the diode to which the bias power supply is connected being provided with a previously detected peak value, thereby detecting a peak of the first analog signal waveform when a voltage across the diode is zero;

a second peak detector having a second diode connected in the normal-biased direction between one of the charge storing cells of the delay element of the first analog dynamic memory circuit and a bias power supply, the end of the diode to which the bias power supply is connected being provided with a previously detected peak value at the other end of the diode, thereby detecting a peak of the second analog signal waveform when a voltage across the diode is zero;

a peak to peak duration detection circuit for measuring respective time of peak to peak durations between two adjacent peaks of the first and the second analog waveforms which are detected by said first and said second peak detectors;

a comparator connected to said peak to peak duration detection circuit, for obtaining a ratio of or a difference between the time of peak to peak durations of the first and the second analog waveforms to output a signal representing the ratio or the difference; and

means for varying a circulating speed of the analog signal waveform stored in the first or the second analog dynamic memory circuit according to the signal representing the ratio or the difference outputted from the comparator.