Quadrature modulation circuit

• US 5,285,479 A
• Filed: 11/13/1991
• Issued: 02/08/1994
• Est. Priority Date: 01/11/1991
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Iwane, Yasushi
• Primary Examiner(s): Kuntz, Curtis
• Assistant Examiner(s): WEBSTER, BRYAN E
• Application Number:
  US07/791,228
• Time in Patent Office: 818 Days
• Field of Search: 375/39, 375/59, 375/60, 375/67, 375/80, 332/103, 364/724.04, 364/724.13
• US Class Current: 375/298
• CPC Class Codes: H04L 25/03859 shaping using look up tables for partial waveforms
• CPC Class Codes: H04L 27/2017 in which the phase changes are non-linear, e.g. generalized and Gaussian minimum shift keying, tamed frequency modulation H04L27/201 takes precedence

Abstract

A quadrature modulation circuit includes a low pass filter which operates by a time division process for the in-phase channel and quadrature-phase channel, and reduces address requirements data using amplitude symmetry of the wave form and/or using symmetry wave form on the time axis. The capacity of the ROM is reduced by half or more and the configuration of the quadrature modulation circuit is simplified.

Claims

1. A quadrature modulation circuit including at least a low pass filter using ROM for limiting the frequency band-width of the in-phase channel and the quadrature channel, at least a D/A converter for converting the digital signal received from said low pass filter to an analog signal, at least a filter for suppressing the aliases outputted from said D/A converter, a quadrature modulator for modulating a carrier signal with the output from said filter:

wherein said low pass filter includes time division process means for time division operation of said filter for the in-phase channel and the quadrature channel with the same band-width limiting characteristic for both the in-phase channel and the quadrature-phase channel.

4. A quadrature modulation circuit of claim 1:

wherein said D/A converter converts the digital signal received from said low pass filter to an analog signal by time division process.

5. A quadrature modulation circuit of claim 1:

wherein said low pass filter, also uses one symbol data in a symbol data as a sign data, and inverts the sign of the remaining symbol data and an output data from a ROM by using said one symbol data.

6. A quadrature modulation circuit of claim 5:

wherein said D/A converter converts the digital signal received from said low pass filter to an analog signal by time division process.

7. A quadrature modulation circuit of claim 5:

wherein said low pass filter, further divides the data into the first half portion and the second half portion, and reads out contents of the ROM for forward direction of the time axis at said first half portion, and for backward direction of the time axis at said second half portion.

8. A quadrature modulation circuit of claim 7:

wherein said D/A converter converts the digital signal received from said low pass filter to an analog signal by time division process.

9. A quadrature modulation circuit of claim 1:

wherein said low pass filter, further divides the data into the first half portion and the second half portion, and reads out contents of the ROM for forward direction of the time axis at said first half portion, and for backward direction of the time axis at said second half portion.

10. A quadrature modulation circuit of claim 9:

wherein said D/A converter converts the digital signal received from said low pass filter to an analog signal by time division process.

2. A quadrature modulation circuit including at least a low pass filter using ROM for limiting the frequency band-width of the in-phase channel and the quadrature channel, at least a D/A converter for converting the digital signal received from said low pass filter to an analog signal, at least a filter for suppressing the aliases outputted from said D/A converter, a quadrature modulator for modulating a carrier signal with the output from said filter:

wherein said low pass filter includes means for using one symbol of data in a symbol data as a sign data, and for inverting the sign of the remaining symbols of data in said symbol data and the output data from said ROM by using said one symbol data.

11. A quadrature modulation circuit of claim 2:

wherein said low pass filter, further divides the data into the first half portion and the second half portion, and reads out contents of the ROM for forward direction of the time axis at said first half portion, and for backward direction of the time axis at said second half portion.

12. A quadrature modulation circuit of claim 11:

wherein said D/A converter converts the digital signal received from said low pass filter to an analog signal by time division process.

3. A quadrature modulation circuit including at least a low pass filter using ROM for limiting the frequency band-width of the in-phase channel and the quadrature channel, at least a D/A converter for converting the digital signal received from said low pass filter to an analog signal, at least a filter for suppressing the aliases outputted from said D/A converter, a quadrature modulator for modulating a carrier signal with the output from said filter:

wherein said low pass filter includes means for dividing the data into a first half portion and a second half portion, and for reading out contents of the ROM along the forward direction of the time axis for said first half portion, and along the backward direction of the time axis for said second half portion.

13. A quadrature modulation circuit including at least a low pass filter for limiting the frequency band-width of the base-band signal to be frequency-modulated, an adder for adding the output of said low pass filter, a latch circuit for adding the output of said adder to the preceding output of said adder, a COS ROM and a SIN ROM for converting the phase value of the output from said adder to an in-phase channel signal and a quadrature channel signal respectively, D/A converters for converting the digital signal received from said COS ROM or SIN ROM respectively, at least a filter for suppressing the aliases outputted from said D/A converter, a quadrature modulator for modulating carrier signal with the output from said filter:

wherein said low pass filter includes means for using one symbol of data in a symbol data as a sign data, and for inverting the sign of the remaining symbols of data in said symbol data and the output data from said ROM by using said one symbol data.

14. A quadrature modulation circuit including at least a low pass filter using ROM for limiting the frequency band-width of the base-band signal to be frequency modulated, an adder for adding the output of said low pass filter, a latch circuit for adding the output of said adder to the preceding output of said adder, a COS ROM and a SIN ROM for converting the phase value of the output from said adder to an in-phase channel signal and a quadrature channel signal respectively, D/A converters for converting the digital signal received from said COS ROM or SIN ROM respectively, at least a filter for suppressing the aliases outputted from said D/A converter, a quadrature modulator for modulating the output from said filter:

wherein said low pass filter includes means for dividing the data into a first half portion and a second half portion, and for reading out contents of the ROM along the forward direction of the time axis for said first half portion, and along the backward direction of the time axis for said second half portion.