Fusion bonding technique for use in fabricating semiconductor devices

• US 5,286,671 A
• Filed: 05/07/1993
• Issued: 02/15/1994
• Est. Priority Date: 05/07/1993
• Status: Expired due to Term

• Current Assignee: Kulite Semiconductor Products Inc
• Original Assignee: Kulite Semiconductor Products Inc
• Inventors: Kurtz, Anthony D., Ned, Alexander A.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/058,400
• Time in Patent Office: 284 Days
• Field of Search: 437/62, 437/63, 437/64, 437/65, 437/901, 437/925, 437/966, 437/974, 148/DIG. 12, 148/DIG. 135, 148/DIG. 150
• US Class Current: 438/50
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: Y10S 148/012 Bonding, e.g. electrostatic for strain gauges

Abstract

A method of bonding a first silicon wafer to a second silicon wafer comprises the steps of diffusing a high conductivity pattern into a surface of a first semiconductor wafer, etching a portion of the surface to raise at least a portion of the pattern, providing a second semiconductor wafer having an insulating layer of a silicon compound disposed thereon, contacting the surface of the pattern to the insulating layer, and bonding the first and second semiconductor wafers at an elevated temperature.

Claims

1. A method of bonding a first silicon wafer to a second silicon wafer comprising the steps of:

diffusing a high conductivity pattern into a surface of a first semiconductor wafer;

etching a portion of said surface to raise at least a portion of said pattern;

providing a second semiconductor wafer having an insulating layer of a silicon compound disposed thereon;

contacting the surface of said pattern to said insulating layer; and

bonding said first and second semiconductor wafers at an elevated temperature.

2. The method according to claim 1, wherein said high conductivity pattern is diffused through a thin layer of an insulating silicon compound.

3. The method according to claim 2, further comprising the step of stripping said thin layer and re-diffusing said high conductivity pattern.

4. The method according to claim 3 wherein said stripping step is performed prior to said etching step.

5. The method according to claim 3, wherein said re-diffusing step is performed by diffusing boron into said first semiconductor wafer, thereby forming a thin layer of B₂ O₃ glass over said pattern.

6. The method according to claim 1, wherein said pattern comprises a circuit pattern.

7. The method according to claim 6, wherein said circuit pattern is a piezoresistive bridge pattern.

8. The method according to claim 7, wherein said pattern is a power circuit pattern.

9. The method according to claim 6, further including the step of etching a surface of said first wafer so that said circuit pattern projects from said first semiconductor wafer.

10. The method according to claim 1, wherein said first and second wafers are bonded at said elevated temperature for less than 15 minutes.

16. The method according to claim 10 where the elevated temperature is at as low as 900°

C. to 1000°

C.

11. A method of fabricating a piezoresistive semiconductor structure for use in a transducer comprising the steps of:

diffusing a piezoresistive pattern into a surface of a first semiconductor wafer;

etching a portion of said surface to raise said piezoresistive pattern;

providing a second semiconductor wafer having an insulating layer of a silicon compound disposed thereon;

contacting the surface of said pattern to said insulating layer; and

bonding said first and second semiconductor wafers at an elevated temperature.

12. The method according to claim 11, wherein said piezoresistive pattern is diffused through a thin insulating layer of a silicon compound of said first semiconductor wafer.

13. The method according to claim 12, further comprising the step of stripping said thin insulating layer and re-diffusing said pattern.

14. The method according to claim 13 wherein said stripping step is performed prior to said etching step.

15. The method according to claim 13, wherein said re-diffusing step is performed by diffusing boron into said first semiconductor wafer, thereby forming a thin layer of B₂ O₃ glass over said piezoresistive pattern.