Timing recovery for variable bit-rate video on asynchronous transfer mode (ATM) networks
First Claim
1. Apparatus for recovering timing in a receiver comprising:
- means for receiving an asynchronous digital signal including system clock reference (SCR) values, an initially received SCR value being a start-up SCR value;
means for extracting said SCR values from said received asynchronous digital signal;
phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output;
means within said phase locked loop means in circuit with said output and being directly supplied with said start-up SCR value for setting said STC signal at said output to said start-up SCR value upon start-up; and
means for supplying said start-up SCR value directly to said means for setting.
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Accused Products
Abstract
Complications of timing recovery in an ATM receiver are overcome by employing a first phase lock loop including a phase comparator, filter, voltage controlled oscillator (VCO) and output counter to lock to systems clock reference (SCR) values which are asynchronously received from a remote ATM transmitter. The SCR values represent the instantaneous values of a system timing clock (STC) at the instant of transmission of the asynchronous SCR values. In the receiver, the output counter is first set to the value of the initial received SCR value so that the derived STC is available for decoding data cells in the initial received packets. Then, so-called Presentation/Decode Time Stamps (PTS/DTS) included in the audio and video data are advantageously employed in conjunction with STC to display properly the received data. Invention, underflow of the receiver data buffers is alleviated by the addition of a "jitter-delay (Dj)" value which causes an extra accumulation of data in the data buffers prior to decoding. Dynamic tracking of the jitter-delay of the channel is obtained by monitoring the fullness of the data buffers and controllably adjusting the jitter-delay, accordingly. The stability of the decoder video timing is enhanced by employing an additional phase locked loop in a video display control which is supplied with a timing error signal. The additional phase locked loop includes a switch, filter, clipper and voltage controlled oscillator (VCO). The switch is enabled in response to output pulses from the VCO to supply the instantaneous error signal input to the filter for each so-called video presentation unit. The VCO has a very stable center frequency which variation is limited by clipping an input control voltage to some small voltage range. Output pulses from the VCO are employed to enable decoding of the presentation units. Faster synchronization is provided at start-up by increasing, via control of the clipper, the allowable voltage range of the VCO.
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Citations
16 Claims
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1. Apparatus for recovering timing in a receiver comprising:
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means for receiving an asynchronous digital signal including system clock reference (SCR) values, an initially received SCR value being a start-up SCR value; means for extracting said SCR values from said received asynchronous digital signal; phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output; means within said phase locked loop means in circuit with said output and being directly supplied with said start-up SCR value for setting said STC signal at said output to said start-up SCR value upon start-up; and means for supplying said start-up SCR value directly to said means for setting. - View Dependent Claims (2, 3)
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4. Apparatus for recovering timing in a receiver comprising:
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means for receiving an asynchronous digital signal including system clock reference (SCR) values, an initially received SCR value being a start-up SCR value; means for extracting said SCR values from said received asynchronous digital signal; phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output, said phase locked loop means including means supplied with said extracted SCR values and said STC signal for generating a phase error signal and means in circuit with said output and being directly supplied with said start-up SCR value for setting said STC signal at said output to said start-up SCR value upon start-up; buffer means for storing data from said received asynchronous signal; means for obtaining a fullness representation of the amount of data stored in said buffer means; means supplied with said phase error signal and said fullness representation for dynamically generating a jitter delay (Dj) value; and means for algebraically subtracting said Dj value from said STC signal to generate a modified representation of said system timing clock signal (STC-Dj). - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. Apparatus for recovering timing in a receiver comprising:
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means for receiving an asynchronous digital signal including system clock reference (SCR) values; means for extracting said SCR values from said received asynchronous digital signal; phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output, said phase locked loop means including means supplied with said extracted SCR values and said STC signal for generating a phase error signal; buffer means for storing data from said received asynchronous signal; means for obtaining a fullness representation of the amount of data stored in said buffer means; means supplied with said phase error signal and said fullness representation for dynamically generating a jitter delay (Dj) value; and means for algebraically subtracting said Dj value from said STC signal to generate a modified representation of said system timing clock signal (STC-Dj). - View Dependent Claims (15, 16)
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Specification