Integrated circuit dual-port memory device having reduced capacitance
First Claim
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1. A dual port memory device, comprising:
- an array of memory cells, said array divided into a first part and a second part along a line in a first direction; and
a plurality of bit lines traversing the array in a second direction perpendicular to the first direction, said bit lines being grouped into a first group corresponding to a first port and a second group corresponding to a second port, with each cell of the array being accessible by bit lines from both the first and second groups, and wherein bit lines in the first group cross over bit lines in the second group in a crossover region between the first and second memory parts.
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Abstract
A dual-port memory device provides for a memory array which is divided approximately in half. Between the two halves of the array, a bit line crossover scheme is provided which minimizes stray capacitance and cross-coupling capacitance between bit lines for the two different ports. A bit line layout plan which minimizes such capacitances causes the data for one of the ports to be inverted in one-half of the array. When data from this half of the array is read or written by such port, the data being read or written must be inverted.
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Citations
18 Claims
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1. A dual port memory device, comprising:
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an array of memory cells, said array divided into a first part and a second part along a line in a first direction; and a plurality of bit lines traversing the array in a second direction perpendicular to the first direction, said bit lines being grouped into a first group corresponding to a first port and a second group corresponding to a second port, with each cell of the array being accessible by bit lines from both the first and second groups, and wherein bit lines in the first group cross over bit lines in the second group in a crossover region between the first and second memory parts. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for transmitting data to and from a dual port memory array, comprising the steps of:
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for a first port, reading data from the array as it is stored therein and writing data into the array to store it thereinto; and for a second port, reading data from a first part of the array as it is stored therein and writing data into the first part of the array to store it thereinto, and reading data from a second part of the array in an inverted form and writing data into the second part of the array in an inverted form to store it thereinto. - View Dependent Claims (11, 12, 13)
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14. A dual port memory device, comprising:
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an array of memory cells organized into rows and columns, wherein the rows are divided into first and second groups; a plurality of bit lines traversing the array in the column direction, wherein said bit lines cross over each other in a crossover region between the first and second row groups, a first set of bit lines associated with a first port and a second set of bit lines associated with a second port; and means connected to the array for inverting data read from the second group of rows by the second port, and for inverting data to be written to the second group of rows through the second port, wherein data communicated to and from the array through the first port is not inverted. - View Dependent Claims (15, 16, 17, 18)
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Specification