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Integrated circuit dual-port memory device having reduced capacitance

  • US 5,287,322 A
  • Filed: 07/17/1991
  • Issued: 02/15/1994
  • Est. Priority Date: 07/17/1991
  • Status: Expired due to Term
First Claim
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1. A dual port memory device, comprising:

  • an array of memory cells, said array divided into a first part and a second part along a line in a first direction; and

    a plurality of bit lines traversing the array in a second direction perpendicular to the first direction, said bit lines being grouped into a first group corresponding to a first port and a second group corresponding to a second port, with each cell of the array being accessible by bit lines from both the first and second groups, and wherein bit lines in the first group cross over bit lines in the second group in a crossover region between the first and second memory parts.

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