Semiconductor memory device

• US 5,287,323 A
• Filed: 03/18/1992
• Issued: 02/15/1994
• Est. Priority Date: 06/27/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takayanagi, Toshinari, Takahashi, Makoto
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/834,231
• Time in Patent Office: 699 Days
• Field of Search: 365/154, 365/156, 365/190, 365/230.05, 365/189.07, 365/189.09, 365/226
• US Class Current: 365/230.05
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

The invention relates to a multi-port memory, wherein data is written into, and read from, a memory cell in multi-port scheme. The memory is designed to solve the problem that the data-writing speed decreases when data-writing and data-reading with respect to the same memory cell conflict with each other. To solve the problem, when data-writing and data-reading with respect to the same memory cell (102) conflict with each other, a bit-line load control circuit (130) is connected, in accordance with address signals and write-enable signals, to bit lines (BLa, /BLa, BLb, /BLb) for selecting the memory cell (102) and turns off bit-line load circuits (117, 127) for supplying a predetermined potential to the bit lines (BLa, /BLa, BLb, /BLb), thereby preventing the data-reading speed from decreasing.

Claims

1. A semiconductor memory device comprising:

memory means for storing data statically;

a first transfer means for transferring the data stored in said memory means to a first bit line, in accordance with the potential of a first word line;

a second transfer means for transferring the data stored in said memory means to a second bit line, in accordance with the potential of a second word line;

potential-holding means connected between said first and second bit lines, on the one hand, and a power-supply potential, for holding the potentials of said bit lines at the power-supply potential; and

potential-holding control means for controlling said potential-holding means in accordance with a plurality of address signals and a plurality of control signals, said potential-holding control means further including;

a circuit which generates a signal for turning off said potential-holding means, when said first and second bit lines are selected by an address signal and data-writing is allowed on one of said first and second bit lines, in accordance with a write-enable signal.

2. The semiconductor memory device according to claim 1, wherein said first transfer means comprises an insulated-gate transistor which has a current path connected, at one end, to a memory node of said memory means and, at the other end, to said first bit line, and a gate connected to said first word line.

3. The semiconductor memory device according to claim 1, wherein said second transfer means comprises an insulated-gate transistor which has a current path connected, at one end, to a memory node of said memory means and, at the other end, to said second bit line, and a gate connected to said second word line.

4. The semiconductor memory device according to claim 1, wherein said potential-holding means comprises an insulated-gate transistor which has a current path connected, at one end, to said second bit line and, at the other end, to the power-supply potential, and a gate connected to said potential-holding control means.

5. A semiconductor memory device comprising:

a memory cell having first and second memory nodes and designed to store data items opposite to each other;

a first pair of insulated-gate transistors, each of which has a current path and a gate, said current path connected, at one end, to said first and second memory nodes, respectively, and, at the other end, to a first pair of bit lines, respectively, and said each gate being connected to a first word line, said first pair of insulated-gate transistors transferring the opposite data items stored in said memory cell to the bit lines of said first pair, respectively, in accordance with the potential of the first word line;

a second pair of insulated-gate transistors each of which has a current path and a gate, said current path connected, at one end, to said first and second memory nodes, respectively, and, at the other end, to a second pair of bit lines, respectively, and said each gate being connected to a second word line, said second pair of insulated-gate transistors transferring the opposite data items stored in said memory cell to the bit lines of said second pair, respectively, in accordance with the potential of the second word line;

third and fourth insulated-gate transistors, each having a current path and a gate, the current paths of the third and fourth insulated-gate transistors being connected, at one end, to the bit lines of said first pair, respectively, and, at the other end, to a power-supply potential;

fifth and sixth insulated-gate transistors, each having a current path and a gate, the current paths of said fifth and sixth insulated gate transistors being connected, at one end, to the bit lines of said second pair, respectively, and, at the other end, to the power-supply potential; and

control means, connected to the gates of the third, fourth, fifth and sixth insulated-gate transistors, for turning off said third, fourth, fifth and sixth insulated-gate transistors in accordance with a plurality of address signals and a plurality of write-enable signals, when data-writing and data-reading with respect to said memory cell conflict with each other.